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DAC081S101

www.ti.com

SNAS323C –JUNE 2005–REVISED FEBRUARY 2013

DAC081S101 8-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output

Check for Samples: DAC081S101

FEATURES

DESCRIPTION

The DAC081S101 is a full-featured, general purpose

• Guaranteed Monotonicity

8-bit voltage-output digital-to-analog converter (DAC)

• Low Power Operation

that can operate from a single +2.7V to 5.5V supply

• Rail-to-Rail Voltage Output

and consumes just 175 µA of current at 3.6 Volts.

The on-chip output amplifier allows rail-to-rail output

• Power-on Reset to Zero Volts Output

swing and the three wire serial interface operates at

• SYNC Interrupt Facility

clock rates up to 30 MHz over the specified supply

• Wide Power Supply Range (+2.7V to +5.5V)

voltage range and is compatible with standard SPI™,

QSPI, MICROWIRE and DSP interfaces. Competitive

• Small Packages

devices are limited to 20 MHz clock rates at supply

• Power Down Feature

voltages in the 2.7V to 3.6V range.

The supply voltage for the DAC081S101 serves as its

APPLICATIONS

voltage reference, providing the widest possible

• Battery-Powered Instruments

output dynamic range. A power-on reset circuit

• Digital Gain and Offset Adjustment

ensures that the DAC output powers up to zero volts

and remains there until there is a valid write to the

• Programmable Voltage & Current Sources

device. A power-down feature reduces power

• Programmable Attenuators

consumption to less than a microWatt.

The low power consumption and small packages of

the DAC081S101 make it an excellent choice for use

in battery operated equipment.

The DAC081S101 is a direct replacement for the

AD5300 and is one of a family of pin compatible

DACs, including the 10-bit DAC101S101 and the 12-

bit DAC121S101. The DAC081S101 operates over

the extended industrial temperature range of −40°C

to +105°C.

Table 1. Key Specifications

VALUE

Resolution 8 bits

DNL +0.04, -0.02 LSB (typ)

Output Settling Time 3 µs (typ)

Zero Code Error 3.8mV (typ)

Full-Scale Error −0.07 %FS (typ)

Normal Mode 0.63 mW (3.6V) / 1.41 mW (5.5V) typ

Power Consumption

Pwr Down Mode 0.14 µW (3.6V) / 0.33 µW (5.5V) typ

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc..

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 DAC081S101 8-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output Check for Samples: DAC081S101 FEATURES DESCRIPTION • • • • • • • • The DAC081S101 is a full-featured, general purpose 8-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes just 175 µA of current at 3.6 Volts.
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com Pin Configuration SOT VOUT 1 6 VSSOP SYNC GND 2 5 SCLK VA 3 4 DIN VA 1 8 GND NC NC 2 7 3 6 DIN SCLK VOUT 4 5 SYNC Block Diagram VA GND POWER-ON RESET DAC081S101 REF(+) REF(-) DAC REGISTER VOUT BUFFER 8-BIT DAC 8 8 POWER-DOWN CONTROL LOGIC INPUT CONTROL LOGIC SCLK SYNC 1k 100k DIN Pin Descriptions Name SOT-23 Pin No. VSSOP Pin No. VOUT 1 4 DAC Analog Output Voltage.
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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 Absolute Maximum Ratings (1) (2) Supply Voltage, VA 6.5V −0.3V to (VA + 0.
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 4 to 251. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.
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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 Electrical Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 4 to 251. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com AC and Timing Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 4 to 251. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.
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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the output code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply.
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated 8 DNL at VA = 3.0V DNL at VA = 5.0V Figure 3. Figure 4. INL at VA = 3.0V INL at VA = 5.0V Figure 5. Figure 6. TUE at VA = 3.0V TUE at VA = 5.0V Figure 7. Figure 8.
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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated DNL vs. VA INL vs. VA Figure 9. Figure 10. 3V DNL vs. fSCLK 5V DNL vs. fSCLK Figure 11. Figure 12. 3V DNL vs. Clock Duty Cycle 5V DNL vs. Clock Duty Cycle Figure 13. Figure 14.
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated 10 3V DNL vs. Temperature 5V DNL vs. Temperature Figure 15. Figure 16. 3V INL vs. fSCLK 5V INL vs. fSCLK Figure 17. Figure 18. 3V INL vs. Clock Duty Cycle 5V INL vs. Clock Duty Cycle Figure 19. Figure 20.
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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated 3V INL vs. Temperature 5V INL vs. Temperature Figure 21. Figure 22. Zero Code Error vs. fSCLK Zero Code Error vs. Clock Duty Cycle Figure 23. Figure 24. Zero Code Error vs. Temperature Full-Scale Error vs. fSCLK Figure 25. Figure 26.
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated 12 Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature Figure 27. Figure 28. Supply Current vs. VA Supply Current vs. Temperature Figure 29. Figure 30. 5V Glitch Response Power-On Reset Figure 31. Figure 32.
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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 4 to 251, unless otherwise stated 3V Wake-Up Time 5V Wake-Up Time Figure 33. Figure 34.
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com FUNCTIONAL DESCRIPTION DAC SECTION The DAC081S101 is fabricated on a CMOS process with an architecture that consists of switches and a resistor string that are followed by an output buffer. The power supply serves as the reference voltage.
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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 Since the SYNC and DIN buffers draw more current when they are high, they should be idled low between write sequences to minimize power consumption. INPUT SHIFT REGISTER The input shift register, Figure 36, has sixteen bits. The first two bits are "don't cares" and are followed by two bits that determine the mode of operation (normal mode or one of three power-down modes).
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com DSP/MICROPROCESSOR INTERFACING Interfacing the DAC081S101 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process. ADSP-2101/ADSP2103 Interfacing Figure 37 shows a serial interface between the DAC081S101 and the ADSP-2101/ADSP2103. The DSP should be set to operate in the SPORT Transmit Alternate Framing Mode.
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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 MICROWIRE DEVICE DAC081S101 CS SYNC SK SCLK SO DIN Figure 40. Microwire Interface USING REFERENCES AS POWER SUPPLIES Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage. Since the DAC081S101 consumes very little power, a reference source may be used as the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability.
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com The minimum resistor value in the circuit of Figure 42 should be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the DAC081S101 draws zero current.
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DAC081S101 www.ti.com SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR.
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DAC081S101 SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013 www.ti.com REVISION HISTORY Changes from Revision B (February 2013) to Revision C • 20 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC081S101CIMK SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DAC081S101CIMK/NOPB SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC081S101CIMK SOT DDC 6 1000 210.0 185.0 35.0 DAC081S101CIMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 SOT DDC 6 3000 210.0 185.0 35.0 VSSOP DGK 8 1000 210.0 185.0 35.0 VSSOP DGK 8 3500 367.0 367.0 35.
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