Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VSSOP 10

OUTA

OUTB

SCLK

REFIN

GND

SON

SYNC

OUTA

OUTB

SCLK

REFIN

GND

VSSOP

SYNC

DAC082S085

www.ti.com

SNAS365F –MAY 2006–REVISED MARCH 2013

DAC082S085 8-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output

Check for Samples: DAC082S085

FEATURES

DESCRIPTION

The DAC082S085 is a full-featured, general purpose

• Ensured Monotonicity

DUAL 8-bit voltage-output digital-to-analog converter

• Low Power Operation

(DAC) that can operate from a single +2.7V to 5.5V

• Rail-to-Rail Voltage Output

supply and consumes 0.6 mW at 3V and 1.6 mW at

5V. The DAC082S085 is packaged in 10-lead SON

• Power-on Reset to 0V

and VSSOP packages. The 10-lead SON package

• Simultaneous Output Updating

makes the DAC082S085 the smallest DUAL DAC in

• Wide power supply range (+2.7V to +5.5V)

its class. The on-chip output amplifier allows rail-to-

rail output swing and the three wire serial interface

• Industry's Smallest Package

operates at clock rates up to 40 MHz over the entire

• Power Down Modes

supply voltage range. Competitive devices are limited

to 25 MHz clock rates at supply voltages in the 2.7V

APPLICATIONS

to 3.6V range. The serial interface is compatible with

standard SPI™, QSPI, MICROWIRE and DSP

• Battery-Powered Instruments

interfaces.

• Digital Gain and Offset Adjustment

The reference for the DAC082S085 serves both

• Programmable Voltage & Current Sources

channels and can vary in voltage between 1V and V

• Programmable Attenuators

providing the widest possible output dynamic range.

The DAC082S085 has a 16-bit input shift register that

KEY SPECIFICATIONS

controls the outputs to be updated, the mode of

operation, the powerdown condition, and the binary

• Resolution: 8 Bits

input data. Both outputs can be updated

• INL: ±0.5 LSB (Max)

simultaneously or individually depending on the

• DNL: +0.18 / -0.13 LSB (Max)

setting of the two mode of operation bits.

• Settling Time: 4.5 µs (Max)

A power-on reset circuit ensures that the DAC output

• Zero Code Error: +15mV (Max)

powers up to zero volts and remains there until there

is a valid write to the device. A power-down feature

• Full-Scale error: -0.75% FS (Max)

reduces power consumption to less than a microWatt

• Supply Power

with three different termination options.

– Normal: 0.6mW (3V) / 1.6 mW (5V) (Typ)

The low power consumption and small packages of

– Power Down: 0.3 µW (3V) / 0.8 µW (5V)

the DAC082S085 make it an excellent choice for use

(Typ)

in battery operated equipment.

The DAC082S085 is one of a family of pin compatible

DACs, including the 10-bit DAC102S085 and the 12-

bit DAC124S085. The DAC082S085 operates over

the extended industrial temperature range of −40°C

to +105°C.

Pin Configuration

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc..

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 DAC082S085 8-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output Check for Samples: DAC082S085 FEATURES DESCRIPTION • • • • • • • • The DAC082S085 is a full-featured, general purpose DUAL 8-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes 0.6 mW at 3V and 1.6 mW at 5V. The DAC082S085 is packaged in 10-lead SON and VSSOP packages.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com Block Diagram VREFIN DAC082S085 REF POWER-ON RESET 8 BIT DAC VOUTA BUFFER 8 2.5k 100k REF DAC REGISTER 8 BIT DAC VOUTB BUFFER 8 8 2.5k POWER-DOWN CONTROL LOGIC INPUT CONTROL LOGIC SYNC SCLK 100k DIN PIN DESCRIPTIONS SON VSSOP Pin No. Symbol Type 1 VA Supply 2 VOUTA Analog Output Channel A Analog Output Voltage. 3 VOUTB Analog Output Channel B Analog Output Voltage. 4 NC Description Power supply input.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) Supply Voltage, VA 6.5V −0.3V to 6.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 3 to 252. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Limits (2) Units (Limits) Resolution 8 Bits (min) Monotonicity 8 Bits (min) ±0.14 ±0.5 LSB (max) +0.04 +0.18 LSB (max) −0.02 −0.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 Electrical Characteristics(1) (continued) The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 3 to 252. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol Typical (2) Limits (2) Units (Limits) ±1 µA (max) VA = 3V 0.9 0.6 V (max) VA = 5V 1.5 0.8 V (max) VA = 3V 1.4 2.1 V (min) VA = 5V 2.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com A.C. and Timing Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 3 to 252. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 Specification Definitions DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 256 = VA / 256. DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change in the output of another DAC.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com Transfer Characteristic FSE 255 x VREFIN 256 GE = FSE - ZE FSE = GE + ZE OUTPUT VOLTAGE ZE 0 0 255 DIGITAL INPUT CODE Figure 1. Input / Output Transfer Characteristic Timing Diagrams | 1 / fSCLK SCLK 1 2 13 tSS tSYNC tCL 14 15 16 tCH tCFSR | SYNC DIN | | tDH DB15 DB0 tDS Figure 2.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 Typical Performance Characteristics VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, unless otherwise stated INL at VA = 3.0V INL at VA = 5.0V Figure 3. Figure 4. DNL at VA = 3.0V DNL at VA = 5.0V Figure 5. Figure 6. INL/DNL vs VREFIN at VA = 3.0V INL/DNL vs VREFIN at VA = 5.0V Figure 7. Figure 8.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, unless otherwise stated 10 INL/DNL vs fSCLK at VA = 2.7V INL/DNL vs VA Figure 9. Figure 10. INL/DNL vs Clock Duty Cycle at VA = 3.0V INL/DNL vs Clock Duty Cycle at VA = 5.0V Figure 11. Figure 12. INL/DNL vs Temperature at VA = 3.0V INL/DNL vs Temperature at VA = 5.0V Figure 13. Figure 14.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, unless otherwise stated Zero Code Error vs. VA Zero Code Error vs. VREFIN Figure 15. Figure 16. Zero Code Error vs. fSCLK Zero Code Error vs. Clock Duty Cycle Figure 17. Figure 18. Zero Code Error vs. Temperature Full-Scale Error vs. VA Figure 19. Figure 20.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, unless otherwise stated 12 Full-Scale Error vs. VREFIN Full-Scale Error vs. fSCLK Figure 21. Figure 22. Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature Figure 23. Figure 24. Supply Current vs. VA Supply Current vs. Temperature Figure 25. Figure 26.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 3 to 252, unless otherwise stated 5V Glitch Response Power-On Reset Figure 27. Figure 28.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com Functional Description DAC SECTION The DAC082S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared by both DACs. For simplicity, a single resistor string is shown in Figure 29.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 SERIAL INTERFACE The three-wire interface is compatible with SPI™, QSPI and MICROWIRE, as well as most DSPs and operates at clock rates up to 40 MHz. See Timing Diagrams for information on a write sequence. A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com Table 1. Power-Down Modes A1 A0 OP1 OP0 0 0 1 1 Operating Mode 0 1 1 1 2.5 kΩ to GND 1 0 1 1 100 kΩ to GND 1 1 1 1 High-Z outputs High-Z outputs The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down modes. However, the contents of the DAC registers are unaffected when in power-down.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 Input Voltage R IDAC VZ IZ 0.1 PF 0.47 PF VA VREFIN LM4050-4.1 or LM4050-5.0 DAC082S085 VOUT = 0V to 5V SYNC DIN SCLK Figure 32. The LM4050 as a power supply The minimum resistor value in the circuit of Figure 32 must be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com LP2980 The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3.0V, 3.3V and 5V versions, among others. VIN Input Voltage LP2980 VOUT ON /OFF 1 PF 0.1 PF VA VREFIN DAC102S085 VOUT = 0V to 5V SYNC DIN SCLK Figure 34. Using the LP2980 regulator Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 DSP/MICROPROCESSOR INTERFACING Interfacing the DAC082S085 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process. ADSP-2101/ADSP2103 Interfacing Figure 36 shows a serial interface between the DAC082S085 and the ADSP-2101/ADSP2103. The DSP should be set to operate in the SPORT Transmit Alternate Framing Mode.
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DAC082S085 SNAS365F – MAY 2006 – REVISED MARCH 2013 www.ti.com Microwire Interface Figure 39 shows an interface between a Microwire compatible device and the DAC082S085. Data is clocked out on the rising edges of the SK signal. As a result, the SK of the Microwire device needs to be inverted before driving the SCLK of the DAC082S085. MICROWIRE DEVICE CS SYNC SK SCLK SO DIN DAC082S085 Figure 39.
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DAC082S085 www.ti.com SNAS365F – MAY 2006 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision E (March 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC082S085CIMM Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC082S085CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC082S085CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC082S085CIMM VSSOP DGS 10 1000 210.0 185.0 35.0 DAC082S085CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 DAC082S085CIMMX/NOP B VSSOP DGS 10 3500 367.0 367.0 35.0 DAC082S085CISD/NOPB WSON DSC 10 1000 210.0 185.0 35.0 WSON DSC 10 4500 367.0 367.0 35.
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