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DAC104S085

www.ti.com

SNAS362F –MAY 2006–REVISED MARCH 2013

DAC104S085/DAC104S085-Q1 10-Bit Micro Power QUAD Digital-to-Analog Converter with

Rail-to-Rail Output

Check for Samples: DAC104S085

FEATURES

DESCRIPTION

The DAC104S085 is a full-featured, general purpose

• Ensured Monotonicity

QUAD 10-bit voltage-output digital-to-analog

• Low Power Operation

converter (DAC) that can operate from a single +2.7V

• Rail-to-Rail Voltage Output

to 5.5V supply and consumes 1.1 mW at 3V and 2.5

mW at 5V. The DAC104S085 is packaged in 10-lead

• Power-on Reset to 0V

SON and VSSOP packages. The 10-lead SON

• Simultaneous Output Updating

package makes the DAC104S085 the smallest QUAD

• Wide power supply range (+2.7V to +5.5V)

DAC in its class. The on-chip output amplifier allows

rail-to-rail output swing and the three wire serial

• Industry's Smallest Package

interface operates at clock rates up to 40 MHz over

• Power Down Modes

the entire supply voltage range. Competitive devices

• AEC-Q100 Grade 1 Qualified

are limited to 25 MHz clock rates at supply voltages

in the 2.7V to 3.6V range. The serial interface is

APPLICATIONS

compatible with standard SPI, QSPI, MICROWIRE

and DSP interfaces.

• Battery-Powered Instruments

The reference for the DAC104S085 serves all four

• Digital Gain and Offset Adjustment

channels and can vary in voltage between 1V and V

• Programmable Voltage & Current Sources

providing the widest possible output dynamic range.

• Programmable Attenuators

The DAC104S085 has a 16-bit input shift register that

controls the outputs to be updated, the mode of

• Automotive

operation, the powerdown condition, and the binary

input data. All four outputs can be updated

KEY SPECIFICATIONS

simultaneously or individually depending on the

• Resolution 10 bits

setting of the two mode of operation bits.

• INL ±2 LSB (max)

A power-on reset circuit ensures that the DAC output

• DNL +0.35 / −0.25 LSB (max)

powers up to zero volts and remains there until there

is a valid write to the device. A power-down feature

• Settling Time 6 μs (max)

reduces power consumption to less than a microWatt

• Zero Code Error +15 mV (max)

with three different termination options.

• Full-Scale Error −0.75 %FS (max)

The low power consumption and small packages of

• Supply Power

the DAC104S085 make it an excellent choice for use

– Normal

in battery operated equipment.

– 1.1 mW (3V)

The DAC104S085 is one of a family of pin compatible

– 2.5 mW (5V) typ

DACs, including the 8-bit DAC084S085 and the 12-bit

DAC124S085. The DAC104S085 operates over the

– Power Down

extended industrial temperature range of −40°C to

– 0.3 μW (3V)

+125°C.

– 0.8 μW (5V) typ

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 DAC104S085/DAC104S085-Q1 10-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output Check for Samples: DAC104S085 FEATURES DESCRIPTION • • • • • • • • • The DAC104S085 is a full-featured, general purpose QUAD 10-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes 1.1 mW at 3V and 2.5 mW at 5V. The DAC104S085 is packaged in 10-lead SON and VSSOP packages.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com Pin Configuration VA 1 VOUTA 2 VOUTB 3 VOUTC 4 VOUTD 5 VA 1 VOUTA 2 VOUTB VOUTC VOUTD 10 SCLK 9 SYNC SON 8 DIN 7 VREFIN 6 GND 10 SCLK 9 3 VSSOP 8 4 7 5 6 SYNC DIN VREFIN GND Block Diagram VREFIN DAC104S085 REF POWER-ON RESET 10 BIT DAC VOUTA BUFFER 10 2.5k 100k REF 10 BIT DAC VOUTB BUFFER 10 DAC REGISTER 2.5k 100k REF 10 BIT DAC VOUTC BUFFER 10 2.5k 100k 10 REF 10 BIT DAC VOUTD BUFFER 10 2.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 PIN DESCRIPTIONS SON VSSOP Pin No. Symbol Type Description 1 VA Supply 2 VOUTA Analog Output Power supply input. Must be decoupled to GND. Channel A Analog Output Voltage. 3 VOUTB Analog Output Channel B Analog Output Voltage. 4 VOUTC Analog Output Channel C Analog Output Voltage. 5 VOUTD Analog Output Channel D Analog Output Voltage.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com (1) (2) Operating Ratings −40°C ≤ TA ≤ +125°C Operating Temperature Range Supply Voltage, VA +2.7V to 5.5V Reference Voltage, VREFIN +1.0V to VA Digital Input Voltage (3) 0.0V to 5.5V Output Load 0 to 1500 pF SCLK Frequency (1) (2) (3) Up to 40 MHz Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 Electrical Characteristics (continued) The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 A.C. and Timing Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com on VREFIN with a full-scale code loaded into the DAC. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 Typical Performance Characteristics VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated INL at VA = 3.0V INL at VA = 5.0V Figure 3. Figure 4. DNL at VA = 3.0V DNL at VA = 5.0V Figure 5. Figure 6. INL/DNL vs VREFIN at VA = 3.0V INL/DNL vs VREFIN at VA = 5.0V Figure 7. Figure 8.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated 10 INL/DNL vs fSCLK at VA = 2.7V INL/DNL vs VA Figure 9. Figure 10. INL/DNL vs Clock Duty Cycle at VA = 3.0V INL/DNL vs Clock Duty Cycle at VA = 5.0V Figure 11. Figure 12. INL/DNL vs Temperature at VA = 3.0V INL/DNL vs Temperature at VA = 5.0V Figure 13. Figure 14.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated Zero Code Error vs. VA Zero Code Error vs. VREFIN Figure 15. Figure 16. Zero Code Error vs. fSCLK Zero Code Error vs. Clock Duty Cycle Figure 17. Figure 18. Zero Code Error vs. Temperature Full-Scale Error vs. VA Figure 19. Figure 20.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated 12 Full-Scale Error vs. VREFIN Full-Scale Error vs. fSCLK Figure 21. Figure 22. Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature Figure 23. Figure 24. Supply Current vs. VA Supply Current vs. Temperature Figure 25. Figure 26.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated 5V Glitch Response Power-On Reset Figure 27. Figure 28.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION DAC SECTION The DAC104S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared by all four DACs. For simplicity, a single resistor string is shown in Figure 29.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 REFERENCE VOLTAGE The DAC104S085 uses a single external reference that is shared by all four channels. The reference pin, VREFIN, is not buffered and has an input impedance of 30 kΩ. It is recommended that VREFIN be driven by a voltage source with low output impedance. The reference voltage range is 1.0V to VA, providing the widest possible output dynamic range.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com POWER-DOWN MODES The DAC104S085 has four power-down modes, two of which are identical. In power-down mode, the supply current drops to 20 µA at 3V and 30 µA at 5V. The DAC104S085 is set in power-down mode by setting OP1 and OP0 to 11. Since this mode powers down all four DACs, the address bits, A1 and A0, are used to select different output terminations for the DAC outputs.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 LM4050 Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the DAC104S085. It is available in 4.096V and 5V versions and comes in a space-saving 3-pin SOT23. Input Voltage R VZ IDAC IZ 0.1 PF 0.47 PF LM4050-4.1 or LM4050-5.0 VA VREFIN DAC104S085 VOUT = 0V to 5V SYNC DIN SCLK Figure 32.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com Input Voltage LP3985 0.1 PF 1 PF 0.01 PF 0.1 PF VA VREFIN DAC104S085 VOUT = 0V to 5V SYNC DIN SCLK Figure 33. Using the LP3985 regulator An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF ceramic capacitor with an ESR requirement of 5mΩ to 500mΩ is required at the output.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 10 pF R2 +5V R1 +5V 10 PF + - 0.1 PF ±5V + DAC104S085 -5V SYNC DIN VOUT SCLK Figure 35. Bipolar Operation The output voltage of this circuit for any code is found to be VO = (VA x (D / 1024) x ((R1 + R2) / R1) - VA x R2 / R1) where • D is the input code in decimal form • With VA = 5V and R1 = R2 VO = (10 x D / 1024) - 5V (5) (6) A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com Table 2. Some Rail-to-Rail Amplifiers AMP PKGS LMC7111 DIP-8 SOT23-5 Typ VOS Typ ISUPPLY 0.9 mV 25 µA LM7301 SO-8 SOT23-5 0.03 mV 620 µA LM8261 SOT23-5 0.7 mV 1 mA DSP/MICROPROCESSOR INTERFACING Interfacing the DAC104S085 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process.
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DAC104S085 www.ti.com SNAS362F – MAY 2006 – REVISED MARCH 2013 68HC11 DAC104S085 PC7 SYNC SCK SCLK MOSI DIN Figure 38. 68HC11 Interface Microwire Interface Figure 39 shows an interface between a Microwire compatible device and the DAC104S085. Data is clocked out on the rising edges of the SK signal. As a result, the SK of the Microwire device needs to be inverted before driving the SCLK of the DAC104S085. MICROWIRE DEVICE CS SYNC SK SCLK SO DIN DAC104S085 Figure 39.
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DAC104S085 SNAS362F – MAY 2006 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC104S085CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC104S085CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC104S085CISD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC104S085CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 DAC104S085CIMMX/NOP B VSSOP DGS 10 3500 367.0 367.0 35.0 DAC104S085CISD/NOPB WSON DSC 10 1000 210.0 185.0 35.0 DAC104S085CISDX/NOP B WSON DSC 10 4500 367.0 367.0 35.0 DAC104S085QIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.
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