Datasheet

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DAC121C081, DAC121C085

www.ti.com

SNAS395D –DECEMBER 2007–REVISED MARCH 2013

DAC121C081/ DAC121C085 12-Bit Micro Power Digital-to-Analog Converter with an I

C-

Compatible Interface

Check for Samples: DAC121C081, DAC121C085

FEATURES

DESCRIPTION

The DAC121C081 is a 12-bit, single channel, voltage-

• Guaranteed Monotonicity to 12-Bits

output digital-to-analog converter (DAC) that operates

• Low Power Operation: 156 µA Max @ 3.3V

from a +2.7V to 5.5V supply. The output amplifier

• Extended Power Supply Range (+2.7V to

allows rail-to-rail output swing and has an 8.5µsec

+5.5V)

settling time. The DAC121C081 uses the supply

voltage as the reference to provide the widest

• I

C-Compatible 2-Wire Interface Which

dynamic output range and typically consumes 132µA

Supports Standard (100kHz), Fast (400kHz),

while operating at 5.0V. It is available in 6-lead SOT

and High Speed (3.4MHz) Modes

and WSON packages and provides three address

• Rail-to-Rail Voltage Output

options (pin selectable).

• Very Small Package

As an alternative, the DAC121C085 provides nine I

addressing options and uses an external reference. It

APPLICATIONS

has the same performance and settling time as the

DAC121C081. It is available in an 8-lead VSSOP.

• Industrial Process Control

• Portable Instruments

The DAC121C081 and DAC121C085 use a 2-wire,

C-compatible serial interface that operates in all

• Digital Gain and Offset Adjustment

three speed modes, including high speed mode

• Programmable Voltage & Current Sources

(3.4MHz). An external address selection pin allows up

• Test Equipment

to three DAC121C081 or nine DAC121C085 devices

per 2-wire bus. Pin compatible alternatives to the

DAC121C081 are available that provide additional

KEY SPECIFICATIONS

address options.

• Resolution: 12 bits

The DAC121C081 and DAC121C085 each have a

• INL: ±8 LSB (max)

16-bit register that controls the mode of operation, the

• DNL: +0.6 / -0.5 LSB (max)

power-down condition, and the output voltage. A

• Settling Time: 8.5 µs (max)

power-on reset circuit ensures that the DAC output

powers up to zero volts. A power-down feature

• Zero Code Error: +10 mV (max)

reduces power consumption to less than a microWatt.

• Full-Scale Error: −0.7 %FS (max)

Their low power consumption and small packages

• Supply Power

make these DACs an excellent choice for use in

battery operated equipment. Each DAC operates over

– Normal: 380 µW (3V) / 730 µW (5V) typ

the extended industrial temperature range of −40°C

– Power Down: 0.5 µW (3V) / 0.9 µW (5V) typ

to +125°C.

The DAC121C081 and DAC121C085 are each part of

a family of pin compatible DACs that also provide 8

and 10 bit resolution. For 8-bit DACs see the

DAC081C081 and DAC081C085. For 10-bit DACs

see the DAC101C081 and DAC101C085.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C is a registered trademark of Phillips Corporation..

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 DAC121C081/ DAC121C085 12-Bit Micro Power Digital-to-Analog Converter with an I2CCompatible Interface Check for Samples: DAC121C081, DAC121C085 FEATURES DESCRIPTION • • • The DAC121C081 is a 12-bit, single channel, voltageoutput digital-to-analog converter (DAC) that operates from a +2.7V to 5.5V supply. The output amplifier allows rail-to-rail output swing and has an 8.5µsec settling time.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com Pin-Compatible Alternatives All devices are fully pin and function compatible.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 PIN DESCRIPTIONS Symbol Type Equivalent Circuit VOUT Analog Output VA Supply Power supply input. For the SOT and WSON versions, this supply is used as the reference. Must be decoupled to GND. GND Ground Ground for all on-chip circuitry. SDA Digital Input/Output Analog Output Voltage. Serial Data bi-directional connection.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) (3) Supply Voltage, VA −0.3V to +6.5V Voltage on any Input Pin −0.3V to +6.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 Package Thermal Resistances (1) (2) (1) (2) Package θJA 6-Lead SOT 250°C/W 6-Lead WSON 190°C/W 8-Lead VSSOP 240°C/W Soldering process must comply with Texas Instruments' Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging (SNOA549) Reflow temperature profiles are different for lead-free packages.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, CL = 200 pF to GND, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 Electrical Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, CL = 200 pF to GND, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com A.C. and Timing Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, RL = Infinity, CL = 200 pF to GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol tHD;DAT Limits (1) (2) Units (Limits) Standard Mode 0 3.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 A.C. and Timing Characteristics (continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, RL = Infinity, CL = 200 pF to GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol Limits (1) (2) Units (Limits) 300 ns (max) 20+0.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com Specification Definitions DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 4096 = VA / 4096. DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC output is not updated. It is measured with a full-scale code change on the data bus.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 Transfer Characteristic FSE 4095 x VREF 4096 GE = FSE - ZE FSE = GE + ZE OUTPUT VOLTAGE ZE 0 0 4095 DIGITAL INPUT CODE Figure 1. Input / Output Transfer Characteristic Timing Diagrams SDA tLOW tf tr tHD;STA tr tf tBUF tSP SCL tSU;STA tHD;STA tHIGH tHD;DAT tSU;DAT REPEATED START START tSU;STO STOP START Figure 2.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated. 12 INL DNL Figure 3. Figure 4. INL/DNL vs Temperature at VA = 3.0V INL/DNL vs Temperature at VA = 5.0V Figure 5. Figure 6. INL/DNL vs VREFIN at VA = 3.0V INL/DNL vs VREFIN at VA = 5.0V Figure 7. Figure 8.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated. INL/DNL vs VA Zero Code Error vs. VA Figure 9. Figure 10. Zero Code Error vs. Temperature Full Scale Error vs. VA Figure 11. Figure 12. Full Scale Error vs. Temperature Total Supply Current vs. VA Figure 13. Figure 14.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated. VREF Supply Current vs. VA Total Supply Current vs. Temperature @ VA = 3V Figure 15. Figure 16. Total Supply Current vs. Temperature @ VA = 5V 5V Glitch Response Figure 17. Figure 18. Power-On Reset Figure 19.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION DAC SECTION The DAC121C081 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. For simplicity, a single resistor string is shown in Figure 20. This string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com The DAC121C085 comes with an external reference supply pin (VREF). For the DAC121C085, it is important that VREF be kept as clean as possible. The Applications Information section describes a handful of ways to drive the reference appropriately. Refer to the USING REFERENCES AS POWER SUPPLIES section for details. SERIAL INTERFACE The I2C-compatible interface operates in all three speed modes.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 Standard-Fast Mode In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is high. The Start condition is always followed by a 7-bit slave address and a Read/Write bit. After these eight bits have been transmitted by the master, SDA is released by the master and the DAC121C081 either ACKs or NACKs the address. If the slave address matches, the DAC121C081 ACKs the master.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com Keep in mind that the address selection inputs (ADR0 and ADR1) are only sampled until the DAC is correctly addressed with a non-broadcast address. At this point, the ADR0 and ADR1 inputs TRI-STATE and the slave address is "locked". Changes to ADR0 and ADR1 will not update the selected slave address until the device is power-cycled. Table 1.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 1 9 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W 0 ACK by DAC121C081 Start by Master Frame 1 Address Byte from Master 0 PD1 PD0 D11 D10 D9 Frame 2 Data Byte from DAC121C081 D8 D7 D6 D5 ACK by Master D4 D3 D2 Frame 3 Data Byte from DAC121C081 D1 D0 NACK by Master Stop by Master Figure 24. Typical Read from the DAC Register DAC REGISTER The DAC register, Figure 25, has sixteen bits.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com ADDITIONAL TIMING INFORMATION: toutz The toutz specification is provided to aid the design of the I2C bus. After the SCL bus is driven low by the I2C master, the SDA bus will be held for a short time by the DAC121C081. This time is referred to as toutz. The following figure illustrates the relationship between the fall of SCL, at the 30% threshold, to the time when the DAC begins to transition the SDA bus.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 Input Voltage R IDAC VZ IZ 0.1 PF 0.47 PF VA VREF LM4050-4.1 or LM4050-5.0 DAC121C081/5 VOUT = 0V to 5V SDA SCL Figure 28. The LM4050 as a power supply The minimum resistor value in the circuit of Figure 28 must be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com LP2980 The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3.0V, 3.3V and 5V versions, among others. VIN Input Voltage VOUT LP2980 1 PF ON /OFF 0.1 PF VA VREF DAC121C081/5 VOUT = 0V to 5V SDA SCL Figure 30. Using the LP2980 regulator Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 DSP/MICROPROCESSOR INTERFACING Interfacing the DAC121C081 to microprocessors and DSPs is quite simple. The following guidelines are offered to simplify the design process. Interfacing to the 2-wire Bus Figure 32 shows a microcontroller interfacing to the DAC121C081 via the 2-wire bus.
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DAC121C081, DAC121C085 SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 www.ti.com LAYOUT, GROUNDING, AND BYPASSING For best accuracy and minimum noise, the printed circuit board containing the DAC121C081 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located on the same board layer. There should be a single ground plane.
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DAC121C081, DAC121C085 www.ti.com SNAS395D – DECEMBER 2007 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC121C081CIMK/NOPB DAC121C081CIMKX/NOP B Package Package Pins Type Drawing DAC121C085CIMM Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DAC121C081CISD/NOPB WSON DAC121C081CISDX/NOP B SPQ NGF 6 1000 178.0 12.4 2.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC121C081CIMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 SOT DDC 6 3000 210.0 185.0 35.0 WSON NGF 6 1000 210.0 185.0 35.0 WSON NGF 6 4500 367.0 367.0 35.0 DAC121C085CIMM VSSOP DGK 8 1000 210.0 185.0 35.0 DAC121C085CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 VSSOP DGK 8 3500 367.0 367.0 35.
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MECHANICAL DATA NGF0006A www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.