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DAC121S101

www.ti.com

SNAS265I –JUNE 2005–REVISED MARCH 2013

DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter

Check for Samples: DAC121S101

FEATURES

DESCRIPTION

The DAC121S101 is a full-featured, general purpose

• DAC121S101Q is AEC-Q100 Grade 1 qualified

12-bit voltage-output digital-to-analog converter

and is manufactured on an Automotive Grade

(DAC) that can operate from a single +2.7V to 5.5V

Flow.

supply and consumes just 177 µA of current at 3.6

• Guaranteed Monotonicity

Volts. The on-chip output amplifier allows rail-to-rail

output swing and the three wire serial interface

• Low Power Operation

operates at clock rates up to 30 MHz over the

• Rail-to-Rail Voltage Output

specified supply voltage range and is compatible with

• Power-on Reset to Zero Volts Output

standard SPI™, QSPI, MICROWIRE and DSP

• Wide Temperature Range of −40°C to +125°C

interfaces. Competitive devices are limited to 20 MHz

clock rates at supply voltages in the 2.7V to 3.6V

• Wide Power Supply Range of +2.7V to +5.5V

range.

• Small Packages

The supply voltage for the DAC121S101 serves as its

• Power Down Feature

voltage reference, providing the widest possible

output dynamic range. A power-on reset circuit

APPLICATIONS

ensures that the DAC output powers up to zero volts

and remains there until there is a valid write to the

• Battery-Powered Instruments

device. A power-down feature reduces power

• Digital Gain and Offset Adjustment

consumption to less than a microWatt.

• Programmable Voltage & Current Sources

The low power consumption and small packages of

• Programmable Attenuators

the DAC121S101 make it an excellent choice for use

• Automotive

in battery operated equipment.

The DAC121S101 is a direct replacement for the

AD5320 and the DAC7512 and is one of a family of

pin compatible DACs, including the 8-bit

DAC081S101 and the 10-bit DAC101S101. The

DAC121S101 operates over the extended industrial

temperature range of −40°C to +105°C while the

DAC121S101Q operates over the Grade 1

automotive temperature range of −40°C to +125°C.

The DAC121S101 is available in a 6-lead SOT and

an 8-lead VSSOP and the DAC121S101Q is

available in the 6-lead SOT only.

Table 1. Key Specifications

VALUE UNIT

Resolution 12 bits

DNL +0.25, -0.15 LSB (typ)

Output Settling Time 8 µs (typ)

Zero Code Error 4 mV (typ)

Full-Scale Error −0.06 %FS (typ)

0.64mW (3.6V) / 1.43mW

Normal Mode

(5.5V) typ

Power Consumption

0.14µW (3.6V) / 0.39µW

Pwr Down Mode

(5.5V) typ

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc..

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter Check for Samples: DAC121S101 FEATURES DESCRIPTION • The DAC121S101 is a full-featured, general purpose 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes just 177 µA of current at 3.6 Volts.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com Pin Configuration VOUT 1 6 SYNC VA 1 8 GND NC NC 2 7 3 6 DIN SCLK VOUT 4 5 SYNC SOT GND 2 5 SCLK VA 3 4 DIN VSSOP Block Diagram VA GND POWER-ON RESET DAC121S101 REF(+) REF(-) DAC REGISTER 12 12-BIT DAC BUFFER VOUT 12 POWER-DOWN CONTROL LOGIC INPUT CONTROL LOGIC SYNC SCLK 1k 100k DIN Pin Functions Pin Descriptions SOT (SOT-23) Pin No. VSSOP Pin No. Symbol 1 4 VOUT DAC Analog Output Voltage.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) Supply Voltage, VA 6.5V −0.3V to (VA + 0.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com Electrical Characteristics The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified. Limits (1) Units (Limits) Resolution 12 Bits (min) Monotonicity 12 Bits (min) ±2.6 ±8 LSB (max) +0.25 +1.0 LSB (max) −0.15 −0.7 LSB (min) ±0.11 ±0.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 Electrical Characteristics (continued) The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified. Symbol Parameter Conditions Typical Limits (1) Units (Limits) (1) POWER REQUIREMENTS IA PC IOUT / IA (3) Normal Mode fSCLK = 30 MHz VA = 5.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com A.C. and Timing Characteristics The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com Timing Diagram SCLK 1 tSUCL 13 14 15 16 tL tH tCS | tSYNC 2 | | 1 / fSCLK | SYNC DB15 DB0 | DIN | | tDHD tSUD Figure 2.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated DNL at VA = 3.0V DNL at VA = 5.0V Figure 3. Figure 4. INL at VA = 3.0V INL at VA = 5.0V Figure 5. Figure 6. TUE at VA = 3.0V TUE at VA = 5.0V Figure 7. Figure 8.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 10 DNL vs. VA INL vs. VA Figure 9. Figure 10. 3V DNL vs. fSCLK 5V DNL vs. fSCLK Figure 11. Figure 12. 3V DNL vs. Clock Duty Cycle 5V DNL vs. Clock Duty Cycle Figure 13. Figure 14.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 3V DNL vs. Temperature 5V DNL vs. Temperature Figure 15. Figure 16. 3V INL vs. fSCLK 5V INL vs. fSCLK Figure 17. Figure 18. 3V INL vs. Clock Duty Cycle 5V INL vs. Clock Duty Cycle Figure 19. Figure 20.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 12 3V INL vs. Temperature 5V INL vs. Temperature Figure 21. Figure 22. Zero Code Error vs. fSCLK Zero Code Error vs. Clock Duty Cycle Figure 23. Figure 24. Zero Code Error vs. Temperature Full-Scale Error vs. fSCLK Figure 25. Figure 26.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature Figure 27. Figure 28. Supply Current vs. VA Supply Current vs. Temperature Figure 29. Figure 30. 5V Glitch Response Power-On Reset Figure 31. Figure 32.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 3V Wake-Up Time 5V Wake-Up Time Figure 33. Figure 34. FUNCTIONAL DESCRIPTION DAC SECTION The DAC121S101 is fabricated on a CMOS process with an architecture that consists of switches and a resistor string that are followed by an output buffer. The power supply serves as the reference voltage.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 VA R R R To Output Amplifier R R Figure 35. DAC Resistor String OUTPUT AMPLIFIER The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com DB15 (MSB) X X DB0 (LSB) PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 1 1 0 Normal Operation 1 1 k:to GND 0 100 k: to GND 1 High Impedance Power-Down Modes Figure 36. Input Register Contents Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 ADSP-2101/ADSP2103 Interfacing Figure 37 shows a serial interface between the DAC121S101 and the ADSP-2101/ADSP2103. The DSP should be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com MICROWIRE DEVICE DAC121S101 CS SYNC SK SCLK SO DIN Figure 40. Microwire Interface USING REFERENCES AS POWER SUPPLIES Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage. Since the DAC121S101 consumes very little power, a reference source may be used as the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 The minimum resistor value in the circuit of Figure 42 should be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the DAC121S101 draws zero current.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR.
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DAC121S101 www.ti.com SNAS265I – JUNE 2005 – REVISED MARCH 2013 Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. The clock and data lines should have controlled impedances.
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DAC121S101 SNAS265I – JUNE 2005 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision H (March 2013) to Revision I • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC121S101CIMK SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DAC121S101CIMK/NOPB SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC121S101CIMK SOT DDC 6 1000 210.0 185.0 35.0 DAC121S101CIMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 SOT DDC 6 3000 210.0 185.0 35.0 DAC121S101CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 DAC121S101QCMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 SOT DDC 6 3000 210.0 185.0 35.
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