Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VSSOP 10

OUTA

OUTB

OUTD

OUTC

SCLK

REFIN

GND

SON

SYNC

OUTA

OUTB

OUTD

OUTC

SCLK

REFIN

GND

VSSOP

SYNC

DAC124S085

www.ti.com

SNAS348F –MAY 2006–REVISED MARCH 2013

DAC124S085 12-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail

Output

Check for Samples: DAC124S085

FEATURES

DESCRIPTION

The DAC124S085 is a full-featured, general purpose

• Ensured Monotonicity

QUAD 12-bit voltage-output digital-to-analog

• Low Power Operation

converter (DAC) that can operate from a single +2.7V

• Rail-to-Rail Voltage Output

to 5.5V supply and consumes 1.1 mW at 3V and 2.4

mW at 5V. The DAC124S085 is packaged in 10-lead

• Power-on Reset to 0V

SON and VSSOP packages.

• Simultaneous Output Updating

The 10-lead SON package makes the DAC124S085

• Wide Power Supply Range (+2.7V to +5.5V)

the smallest QUAD DAC in its class. The on-chip

• Industry's Smallest Package

output amplifier allows rail-to-rail output swing and the

• Power Down Modes

three wire serial interface operates at clock rates up

to 40 MHz over the entire supply voltage range.

Competitive devices are limited to 25 MHz clock rates

APPLICATIONS

at supply voltages in the 2.7V to 3.6V range. The

• Battery-Powered Instruments

serial interface is compatible with standard SPI,

• Digital Gain and Offset Adjustment

QSPI, MICROWIRE and DSP interfaces.

• Programmable Voltage & Current Sources

The reference for the DAC124S085 serves all four

• Programmable Attenuators

channels and can vary in voltage between 1V and V

providing the widest possible output dynamic range.

The DAC124S085 has a 16-bit input shift register that

KEY SPECIFICATIONS

controls the outputs to be updated, the mode of

• Resolution: 12 Bits

operation, the powerdown condition, and the binary

• INL: ±8 LSB (Max)

input data. All four outputs can be updated

simultaneously or individually depending on the

• DNL: +0.7 / −0.5 LSB (Max)

setting of the two mode of operation bits.

• Setting Time: 8.5 µs (Max)

A power-on reset circuit ensures that the DAC output

• Zero Code Error: +15 mV (Max)

powers up to zero volts and remains there until there

• Full-Scale Error: −0.75 %FS (Max)

is a valid write to the device. A power-down feature

• Supply Power:

reduces power consumption to less than a microWatt

with three different termination options.

– Normal: 1.1 mW (3V) / 2.4 mW (5V) Typ

– Power Down: 0.3 µW (3V) / 0.8 µW (5V) Typ

The low power consumption and small packages of

the DAC124S085 make it an excellent choice for use

in battery operated equipment.

The DAC124S085 is one of a family of pin compatible

DACs, including the 8-bit DAC084S085 and the 10-bit

DAC104S085. The DAC124S085 operates over the

extended industrial temperature range of −40°C to

+105°C.

Pin Configuration

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 DAC124S085 12-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output Check for Samples: DAC124S085 FEATURES DESCRIPTION • • • • • • • • The DAC124S085 is a full-featured, general purpose QUAD 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes 1.1 mW at 3V and 2.4 mW at 5V. The DAC124S085 is packaged in 10-lead SON and VSSOP packages.
PAGE 2
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com Block Diagram VREFIN DAC124S085 REF POWER-ON RESET 12 BIT DAC VOUTA BUFFER 12 2.5k 100k REF 12 BIT DAC VOUTB BUFFER 12 DAC REGISTER 2.5k 100k REF 12 BIT DAC VOUTC BUFFER 12 2.5k 100k 12 REF 12 BIT DAC VOUTD BUFFER 12 2.5k INPUT CONTROL LOGIC SYNC SCLK 100k POWER-DOWN CONTROL LOGIC DIN Pin Descriptions SON VSSOP Pin No. 2 Symbol Type Description 1 VA Supply 2 VOUTA Analog Output Power supply input.
PAGE 3
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage, VA 6.5V −0.3V to 6.
PAGE 4
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com Package Thermal Resistances (1) (2) (1) (2) Package θJA 10-Lead VSSOP 240°C/W 10-Lead SON 250°C/W Soldering process must comply with Texas Instruments' Reflow Temperature Profile specifications. Refer to http://www.ti.com/lit/SNOA549 Reflow temperature profiles are different for lead-free packages. Electrical Characteristics The following specifications apply for VA = +2.7V to +5.
PAGE 5
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 Electrical Characteristics (continued) The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol Parameter Conditions Units (Limits) Typical (1) Limits (1) 0.2 1.
PAGE 6
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com A.C. and Timing Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
PAGE 7
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 Specification Definitions DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 4096 = VA / 4096. DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change in the output of another DAC.
PAGE 8
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com Transfer Characteristic FSE 4095 x VA 4096 GE = FSE - ZE FSE = GE + ZE OUTPUT VOLTAGE ZE 0 0 4095 DIGITAL INPUT CODE Figure 1. Input / Output Transfer Characteristic Timing Diagrams | 1 / fSCLK SCLK 1 2 13 tSS tSYNC tCL 14 15 16 tCH tCFSR | SYNC DIN | | tDH DB15 DB0 tDS Figure 2.
PAGE 9
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 Typical Performance Characteristics VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated INL at VA = 3.0V INL at VA = 5.0V Figure 3. Figure 4. DNL at VA = 3.0V DNL at VA = 5.0V Figure 5. Figure 6. INL/DNL vs VREFIN at VA = 3.0V INL/DNL vs VREFIN at VA = 5.0V Figure 7. Figure 8.
PAGE 10
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 10 INL/DNL vs fSCLK at VA = 2.7V INL/DNL vs VA Figure 9. Figure 10. INL/DNL vs Clock Duty Cycle at VA = 3.0V INL/DNL vs Clock Duty Cycle at VA = 5.0V Figure 11. Figure 12. INL/DNL vs Temperature at VA = 3.0V INL/DNL vs Temperature at VA = 5.0V Figure 13. Figure 14.
PAGE 11
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated Zero Code Error vs. VA Zero Code Error vs. VREFIN Figure 15. Figure 16. Zero Code Error vs. fSCLK Zero Code Error vs. Clock Duty Cycle Figure 17. Figure 18. Zero Code Error vs. Temperature Full-Scale Error vs. VA Figure 19. Figure 20.
PAGE 12
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 12 Full-Scale Error vs. VREFIN Full-Scale Error vs. fSCLK Figure 21. Figure 22. Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature Figure 23. Figure 24. Supply Current vs. VA Supply Current vs. Temperature Figure 25. Figure 26.
PAGE 13
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 5V Glitch Response Power-On Reset Figure 27. Figure 28. Functional Description DAC SECTION The DAC124S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer.
PAGE 14
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com VA R R R To Output Amplifier R R Figure 29. DAC Resistor String OUTPUT AMPLIFIERS The output amplifiers are rail-to-rail, providing an output voltage range of 0V to VA when the reference is VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC.
PAGE 15
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 INPUT SHIFT REGISTER The input shift register, Figure 30, has sixteen bits. The first two bits are address bits. They determine whether the register data is for DAC A, DAC B, DAC C, or DAC D.
PAGE 16
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com Table 1. Power-Down Modes A1 A0 OP1 OP0 0 0 1 1 Operating Mode 0 1 1 1 2.5 kΩ to GND 1 0 1 1 100 kΩ to GND 1 1 1 1 High-Z outputs High-Z outputs The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down modes. However, the contents of the DAC registers are unaffected when in power-down.
PAGE 17
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 Input Voltage R IDAC VZ IZ 0.1 PF 0.47 PF LM4050-4.1 or LM4050-5.0 VA VREFIN DAC124S085 VOUT = 0V to 5V SYNC DIN SCLK Figure 32. The LM4050 as a power supply The minimum resistor value in the circuit of Figure 32 must be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating.
PAGE 18
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com LP2980 The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3.0V, 3.3V and 5V versions, among others. VIN Input Voltage VOUT LP2980 ON /OFF 1 PF 0.1 PF VA VREFIN DAC124S085 VOUT = 0V to 5V SYNC DIN SCLK Figure 34. Using the LP2980 regulator Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability.
PAGE 19
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 Table 2. Some Rail-to-Rail Amplifiers AMP PKGS LMC7111 DIP-8 SOT23-5 Typ VOS Typ ISUPPLY 0.9 mV 25 µA LM7301 SO-8 SOT23-5 0.03 mV 620 µA LM8261 SOT23-5 0.7 mV 1 mA DSP/MICROPROCESSOR INTERFACING Interfacing the DAC124S085 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process.
PAGE 20
DAC124S085 SNAS348F – MAY 2006 – REVISED MARCH 2013 www.ti.com 68HC11 DAC124S085 PC7 SYNC SCK SCLK MOSI DIN Figure 38. 68HC11 Interface Microwire Interface Figure 39 shows an interface between a Microwire compatible device and the DAC124S085. Data is clocked out on the rising edges of the SK signal. As a result, the SK of the Microwire device needs to be inverted before driving the SCLK of the DAC124S085. MICROWIRE DEVICE CS SYNC SK SCLK SO DIN DAC124S085 Figure 39.
PAGE 21
DAC124S085 www.ti.com SNAS348F – MAY 2006 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision E (March 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 22
PACKAGE OPTION ADDENDUM www.ti.
PAGE 23
PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 24
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC124S085CIMM Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC124S085CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC124S085CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 25
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC124S085CIMM VSSOP DGS 10 1000 210.0 185.0 35.0 DAC124S085CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 DAC124S085CIMMX/NOP B VSSOP DGS 10 3500 367.0 367.0 35.0 DAC124S085CISD/NOPB WSON DSC 10 1000 210.0 185.0 35.0 WSON DSC 10 4500 367.0 367.0 35.
PAGE 26
PAGE 27
PAGE 28
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.