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DAC128S085

www.ti.com

SNAS407F –AUGUST 2007–REVISED MARCH 2013

DAC128S085 12-Bit Micro Power OCTAL Digital-to-Analog Converter with Rail-to-Rail

Outputs

Check for Samples: DAC128S085

FEATURES

DESCRIPTION

The DAC128S085 is a full-featured, general purpose

• Guaranteed Monotonicity

OCTAL 12-bit voltage-output digital-to-analog

• Low Power Operation

converter (DAC) that can operate from a single +2.7V

• Rail-to-Rail Voltage Output

to +5.5V supply and consumes 1.95 mW at 3V and

4.85 mW at 5V. The DAC128S085 is packaged in a

• Daisy Chain Capability

16-lead WQFN package and a 16-lead TSSOP

• Power-on Reset to 0V

package. The WQFN package makes the

• Simultaneous Output Updating

DAC128S085 the smallest OCTAL DAC in its class.

The on-chip output amplifiers allow rail-to-rail output

• Individual Channel Power Down Capability

swing and the three wire serial interface operates at

• Wide power supply range (+2.7V to +5.5V)

clock rates up to 40 MHz over the entire supply

• Dual Reference Voltages with range of 0.5V to

voltage range. Competitive devices are limited to 25

A MHz clock rates at supply voltages in the 2.7V to

3.6V range. The serial interface is compatible with

• Operating Temperature Range of −40°C to

standard SPI™, QSPI, MICROWIRE and DSP

+125°C

interfaces. The DAC128S085 also offers daisy chain

• Industry's Smallest Package

operation where an unlimited number of

DAC128S085s can be updated simultaneously using

APPLICATIONS

a single serial interface.

• Battery-Powered Instruments

There are two references for the DAC128S085. One

• Digital Gain and Offset Adjustment

reference input serves channels A through D while

the other reference serves channels E through H.

• Programmable Voltage & Current Sources

Each reference can be set independently between

• Programmable Attenuators

0.5V and V

, providing the widest possible output

• Voltage Reference for ADCs

dynamic range. The DAC128S085 has a 16-bit input

shift register that controls the mode of operation, the

• Sensor Supply Voltage

power-down condition, and the DAC channels'

• Range Detectors

updated simultaneously or individually.

KEY SPECIFICATIONS

A power-on reset circuit ensures that the DAC

• Resolution 12 bits

outputs power up to zero volts and remain there until

• INL ±8 LSB (max)

there is a valid write to the device. The power-down

feature of the DAC128S085 allows each DAC to be

• DNL +0.75 / −0.4 LSB (max)

independently powered with three different

• Settling Time 8.5 μs (max)

termination options. With all the DAC channels

• Zero Code Error +15 mV (max)

powered down, power consumption reduces to less

than 0.3 µW at 3V and less than 1 µW at 5V. The low

• Full-Scale Error −0.75 %FSR (max)

power consumption and small packages of the

• Supply Power

DAC128S085 make it an excellent choice for use in

– 1.95 mW (3V) / 4.85 mW (5V) typ

battery operated equipment.

– Power Down 0.3 μW (3V) / 1 μW (5V) typ

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc..

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

PAGE 1
DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 DAC128S085 12-Bit Micro Power OCTAL Digital-to-Analog Converter with Rail-to-Rail Outputs Check for Samples: DAC128S085 FEATURES DESCRIPTION • • • • • • • • • The DAC128S085 is a full-featured, general purpose OCTAL 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to +5.5V supply and consumes 1.95 mW at 3V and 4.85 mW at 5V.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com DESCRIPTION (CONTINUED) The DAC128S085 is one of a family of pin compatible DACs, including the 8-bit DAC088S085 and the 10-bit DAC108S085. All three parts are offered with the same pinout, allowing system designers to select a resolution appropriate for their application without redesigning their printed circuit board. The DAC128S085 operates over the extended industrial temperature range of −40°C to +125°C.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 PIN CONFIGURATION SCLK SYNC DIN DOUT 13 14 15 16 VOUTA 1 12 VOUTE VOUTB 2 11 VOUTF DAC128S085 VOUTC 3 10 VOUTG VOUTD 4 9 VOUTH DIN 1 16 DOUT 2 15 SYNC VOUTA 3 14 VOUTE SCLK 8 7 6 5 GND VREF2 VREF1 VA VOUTB 4 13 VOUTF VOUTC 5 12 VOUTG VOUTD 6 11 VOUTH VA 7 10 GND VREF1 8 9 DAC128S085 VREF2 Pin Descriptions WQFN Pin No. TSSOP Pin No.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) Supply Voltage, VA 6.5V −0.3V to 6.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 Package Thermal Resistances (continued) θJA Package Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/lit/SNOA549. (1) (1) Reflow temperature profiles are different for lead-free packages. Electrical Characteristics The following specifications apply for VA = +2.7V to +5.5V, VREF1 = VREF2 = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply for VA = +2.7V to +5.5V, VREF1 = VREF2 = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol Parameter Conditions Typical Input Range Minimum VREF1,2 0.5 Input Range Maximum Input Impedance Limits (1) Units (Limits) 2.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 Electrical Characteristics (continued) The following specifications apply for VA = +2.7V to +5.5V, VREF1 = VREF2 = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com TIMING DIAGRAMS | | 1 / fSCLK SCLK 1 tSYNC 2 15 tCL tSS 16 1 2 15 16 tCH | SYNC | tSH DB15 DB0 | | DIN1 | | tDH DB15 DB0 tDS | | tDH DIN2/DOUT1 | DB15 DB0 tDS Figure 1. Serial Timing Diagram Specification Definitions DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 4096 = VA / 4096.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave on VREF1,2 with the DAC code at full-scale. NOISE SPECTRAL DENSITY is the internally generated random noise. It is measured by loading the DAC to mid-scale and measuring the noise at the output.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS VA = +2.7V to +5.5V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C, unless otherwise stated 10 INL vs Code DNL vs Code Figure 3. Figure 4. INL/DNL vs VREF INL/DNL vs fSCLK Figure 5. Figure 6. INL/DNL vs VA INL/DNL vs Temperature Figure 7. Figure 8.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VA = +2.7V to +5.5V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C, unless otherwise stated Zero Code Error vs. VA Zero Code Error vs. VREF Figure 9. Figure 10. Zero Code Error vs. fSCLK Zero Code Error vs. Temperature Figure 11. Figure 12. Full-Scale Error vs. VA Full-Scale Error vs. VREF Figure 13. Figure 14.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) VA = +2.7V to +5.5V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C, unless otherwise stated 12 Full-Scale Error vs. fSCLK Full-Scale Error vs. Temperature Figure 15. Figure 16. IVA vs. VA IVA vs. Temperature Figure 17. Figure 18. IVREF vs. VREF IVREF vs. Temperature Figure 19. Figure 20.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VA = +2.7V to +5.5V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C, unless otherwise stated Settling Time Glitch Response Figure 21. Figure 22. Wake-Up Time DAC-to-DAC Crosstalk Figure 23. Figure 24. Power-On Reset Multiplying Bandwidth Figure 25. Figure 26.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION DAC ARCHITECTURE The DAC128S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltages are externally applied at VREF1 for DAC channels A through D and VREF2 for DAC channels E through H. For simplicity, a single resistor string is shown in Figure 27.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 OUTPUT AMPLIFIERS The output amplifiers are rail-to-rail, providing an output voltage range of 0V to VA when the reference is VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com SYNC SCLK DIN SYNC SCLK SYNC SCLK SYNC SCLK DIN DOUT DIN DOUT DIN DOUT DAC 1 DAC 2 DAC 3 Figure 30. Daisy Chain Configuration The serial data output pin, DOUT, is available on the DAC128S085 to allow daisy-chaining of multiple DAC128S085 devices in a system. In a write sequence, DOUT remains low for the first fourteen falling edges of SCLK before going high on the fifteenth falling edge.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 When the DAC128S085 first powers up, the DAC is in WRM. In WRM, the registers of each individual DAC channel can be written to without causing the DAC outputs to be updated. This is accomplished by setting DB15 to "0", specifying the DAC register to be written to in DB[14:12], and entering the new DAC register setting in DB[11:0] (see Table 2).The DAC128S085 remains in WRM until the mode of operation is changed to WTM.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com Table 2. Commands Impacted by WRM and WTM DB15 DB[14:12] DB[11:0] 0 000 D11 D10 ... D1 D0 WRM: D[11:0] written to ChA's data register only WTM: ChA's output is updated by data in D[11:0] Description of Mode 0 001 D11 D10 ... D1 D0 WRM: D[11:0] written to ChB's data register only WTM: ChB's output is updated by data in D[11:0] 0 010 D11 D10 ...
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 POWER-ON RESET The power-on reset circuit controls the output voltages of the eight DACs during power-up. Upon application of power, the DAC registers are filled with zeros and the output voltages are set to 0V. The outputs remain at 0V until a valid write sequence is made. POWER-DOWN MODES The DAC128S085 has three power-down modes where different output terminations can be selected (see Table 4).
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION EXAMPLES PROGRAMMING THE DAC128S085 This section will present the step-by-step instructions for programming the serial input register. Updating DAC Outputs Simultaneously When the DAC128S085 is first powered on, the DAC is operating in Write Register Mode (WRM). Operating in WRM allows the user to program the registers of multiple DAC channels without causing the DAC outputs to be updated.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 Input Voltage LM4132-4.1 C1 + 4.7 PF C3 0.1 PF + C2 4.7 PF VA VREF1,2 DAC128S085 SYNC DIN VOUT = 0V to 4.095V SCLK Figure 32. The LM4132 as a power supply LM4050 Available with accuracy of ±0.1%, the LM4050 shunt reference is also a good choice as a reference for the DAC128S085. It is available in 4.096V and 5V versions and comes in a space-saving 3-pin SOT-23. Input Voltage R VZ IDAC IZ 0.1 PF 1 PF LM4050-4.1 or LM4050-5.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com Input Voltage LP3985-5.0 1 PF 1 PF 0.1 PF 0.01 PF VA VREF1,2 DAC128S085 SYNC VOUT = 0V to 5V DIN SCLK Figure 34. Using the LP3985 regulator An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF ceramic capacitor with an ESR requirement of 5mΩ to 500mΩ is required at the output.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 10 pF R2 +5V R1 +5V 10 PF + - 0.1 PF ±5V + VA / VREF1,2 -5V DAC128S085 VOUT SYNC DIN SCLK Figure 36. Bipolar Operation The output voltage of this circuit for any code is found to be VO = (VA x (D / 4096) x ((R1 + R2) / R1) - VA x R2 / R1) (6) where D is the input code in decimal form.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com APPLICATION CIRCUITS The following figures are examples of the DAC128S085 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. Industrial Application Figure 38 shows the DAC128S085 controlling several different circuits in an industrial setting.
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DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 experiences a 5% increase to its reference voltage. This causes the size of the ADC's least significant bit (LSB) to increase by 5%. As a result of the sensor's gain increasing by 5% and the LSB size of the ADC increasing by the same 5%, there is no net effect on the circuit's performance. It is assumed that the amplifier gain is set low enough to allow for a 5% increase in the sensor output.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com ADSP-2101/ ADSP2103 TFS DT SCLK DAC128S085 SYNC DIN SCLK Figure 41. ADSP-2101/2103 Interface 80C51/80L51 Interface A serial interface between the DAC128S085 and the 80C51/80L51 microcontroller is shown in Figure 42. The SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line P3.3. This line is taken low when data is transmitted to the DAC128S085.
PAGE 27
DAC128S085 www.ti.com SNAS407F – AUGUST 2007 – REVISED MARCH 2013 LAYOUT, GROUNDING, AND BYPASSING For best accuracy and minimum noise, the printed circuit board containing the DAC128S085 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located in the same board layer. A single ground plane is preferred if digital return current does not flow through the analog ground area.
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DAC128S085 SNAS407F – AUGUST 2007 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 28 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC128S085CIMTX/NOP B Package Package Pins Type Drawing TSSOP DAC128S085CISQ/NOPB WQFN DAC128S085CISQX/NOP B WQFN SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 RGH 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 RGH 16 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device DAC128S085CIMTX/NOP B DAC128S085CISQ/NOPB DAC128S085CISQX/NOP B Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSSOP PW 16 2500 367.0 367.0 35.0 WQFN RGH 16 1000 210.0 185.0 35.0 WQFN RGH 16 4500 367.0 367.0 35.
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PAGE 34
PACKAGE OUTLINE RGH0016A WQFN - 0.8 mm max height SCALE 3.500 WQFN 4.1 3.9 B A PIN 1 INDEX AREA 0.5 0.3 0.3 0.2 4.1 3.9 DETAIL OPTIONAL TERMINAL TYPICAL C 0.8 MAX SEATING PLANE (0.1) TYP 2.6 0.1 5 8 SEE TERMINAL DETAIL 12X 0.5 4 9 4X 1.5 1 12 16X PIN 1 ID (OPTIONAL) 13 16 16X 0.3 0.2 0.1 0.05 C A C B 0.5 0.3 4214978/A 10/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
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EXAMPLE BOARD LAYOUT RGH0016A WQFN - 0.8 mm max height WQFN ( 2.6) SYMM 16 13 SEE DETAILS 16X (0.6) 16X (0.25) 1 12 (0.25) TYP SYMM (3.8) (1) 9 4 12X (0.5) 5X ( 0.2) VIA 8 5 (1) (3.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND METAL SOLDER MASK OPENING METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214978/A 10/2013 NOTES: (continued) 4.
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EXAMPLE STENCIL DESIGN RGH0016A WQFN - 0.8 mm max height WQFN SYMM (0.675) METAL TYP 13 16 16X (0.6) 16X (0.25) 12 1 (0.25) TYP (0.675) SYMM (3.8) 12X (0.5) 9 4 8 5 4X (1.15) (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 78% PRINTED SOLDER COVERAGE BY AREA SCALE:15X 4214978/A 10/2013 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.
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