Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) LLP 16 EP

DAC161S055

www.ti.com

SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012

DAC161S055 Precision 16-Bit, Buffered Voltage-Output DAC

Check for Samples: DAC161S055

FEATURES

DESCRIPTION

The DAC161S055 is a precision 16-bit, buffered

• 16-bit DAC with a Two-buffer SPI Interface

voltage output Digital-to-Analog Converter (DAC) that

• Asynchronous Load DAC and Reset Pins

operates from a 2.7V to 5.25V supply with a separate

• Compatibility with 1.8V Controllers

I/O supply pin that operates down to 1.7V. The on-

chip precision output buffer provides rail-to-rail output

• Buffered Voltage Output with Rail-to-Rail

swing and has a typical settling time of 5 µsec. The

Capability

external voltage reference can be set between 2.5V

• Wide Voltage Reference Range of +2.5V to V

and V

(the analog supply voltage), providing the

• Wide Temperature Range of −40°C to +105°C

widest dynamic output range possible.

• Packaged in a 16-pin WQFN

The 4-wire SPI compatible interface operates at clock

rates up to 20 MHz. The part is capable of Diasy

APPLICATIONS

Chain and Data Read Back. An on board power-on-

reset (POR) circuit ensures the output powers up to a

• Process Control

known state.

• Automatic Test Equipment

The DAC161S055 features a power-up value pin

• Programmable Voltage Sources

(MZB), a load DAC pin (LDACB) and a DAC clear

• Communication Systems

(CLRB) pin. MZB sets the startup output voltage to

• Data Acquisition either GND or mid-scale. LDACB updates the output,

allowing multiple DACs to update their outputs

• Industrial PLCs

simultaneously. CLRB can be used to reset the

• Portable Battery Powered Instruments

output signal to the value determined by MZB.

The DAC161S055 has a power-down option that

KEY SPECIFICATIONS

reduces power consumption when the part is not in

• Resolution (Specified Monotonic) 16 bits

use. It is available in a 16-lead WQFN package.

• INL ±3 LSB (max)

• Very Low Output Noise 120 nV/√Hz (typ)

• Glitch Impulse 7 nV-s (typ)

• Output Settling Time 5 µs (typ)

• Power Consumption 5.5 mW at 5.25 V (max)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 DAC161S055 Precision 16-Bit, Buffered Voltage-Output DAC Check for Samples: DAC161S055 FEATURES DESCRIPTION • • • • The DAC161S055 is a precision 16-bit, buffered voltage output Digital-to-Analog Converter (DAC) that operates from a 2.7V to 5.25V supply with a separate I/O supply pin that operates down to 1.7V. The onchip precision output buffer provides rail-to-rail output swing and has a typical settling time of 5 µsec.
PAGE 2
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 www.ti.
PAGE 3
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 PIN DESCRIPTIONS (continued) Pin Name Pin # WQFN-16 ESD Structure Type Function and Connection TO OUT DRIVE VOUT 2 Analog Output DAC output. VREF 6 Analog Input GND 7 Ground SDI 11 Digital Input SPI data input . CSB 12 Digital Input Chip select signal for SPI interface. On the falling edge of CSB the chip begins to accept data and output data with the SCLK signal. This pin is active low.
PAGE 4
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) −0.3V to 6.0V Supply Voltage, VA −0.3V to VA+0.3V Supply Voltage VDDIO 6V, −0.3V Any pin relative to GND Voltage on MZB or VREF Input Pin Voltage on any other Input Pin (3) −0.3V to VA+0.
PAGE 5
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 ELECTRICAL CHARACTERISTICS The following specifications apply for VA = 2.7V to 5.25V, VDDIO = VA, VREF = 2.5V to VA, RL = 10k to GND, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 512 to 65023. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits apply to TA = 25°C, unless otherwise specified.
PAGE 6
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) The following specifications apply for VA = 2.7V to 5.25V, VDDIO = VA, VREF = 2.5V to VA, RL = 10k to GND, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 512 to 65023. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits apply to TA = 25°C, unless otherwise specified.
PAGE 7
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 DIGITAL INTERFACE TIMING CHARACTERISTICS These specifications apply for VA = 2.7V to 5.25V, VDDIO = 1.7V to VA, CL = 200 pF. Boldface limits apply for TA = −40°C to 105°C. All other limits apply to TA = 25°C, unless otherwise specified.
PAGE 8
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 50% SCLK CSB www.ti.com CSB 50% 50% 50% 50% 50% LDACB tCSH tCSS CSB 50% tLDACS 50% tLDAC 50% SCLK SDO 50% SDO tDO tZSDO SCLK tSDOZ 50% CSB 50% SDI 50% CLRB tDS tCLRS tDH 50% tCLR Figure 2. Timing Parameter Specifics TRANSFER CHARACTERISTICS FSE 65535 x VA 65536 GE = FSE - ZE FSE = GE + ZE OUTPUT VOLTAGE ZE 0 0 65535 DIGITAL INPUT CODE Figure 3.
PAGE 9
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 SPECIFICATION DEFINITIONS DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 65536. DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.
PAGE 10
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS DNL at VA = 3.0V 0.75 0.75 0.50 0.50 0.25 0.00 -0.25 0.25 0.00 -0.25 -0.50 -0.50 -0.75 -0.75 -1.00 -1.00 0 16,384 32,768 49,152 65,536 0 32,768 49,152 OUTPUT CODE Figure 4. Figure 5. 0.75 0.50 0.50 INL (LSBs) 0.75 0.25 0.00 65,536 INL at VA = 5.0V 1.00 -0.25 0.25 0.00 -0.25 -0.50 -0.50 -0.75 -0.75 -1.00 -1.
PAGE 11
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) DNL vs. VREF, VA=5V INL vs. VREF, VA=5V 1.100 0.8 0.7 0.576 -DNL +DNL 0.2 -INL +INL INL (LSBs) DNL (LSBs) 0.4 0.0 0.051 -0.2 -0.4 -0.475 -0.6 -0.8 2.00 2.65 3.30 3.95 4.60 5.25 -1.000 2.00 2.65 3.30 3.95 4.60 5.25 VREF(V) VREF(V) Figure 10. Figure 11. DNL vs. Temperature, VA=5V, VREF=4.096 INL vs. Temperature, VA=5V, VREF=4.096 0.8 1.00 0.7 0.75 0.0 -0.
PAGE 12
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) IVA vs VA 890 460 230 NO CLOCK, 5V CLOCKING, 5V NO CLOCK, 3.3V CLOCKING, 3.3V 790 740 690 0 3 4 5 640 -50 6 -10 Figure 16. Figure 17. IREF vs VREF VA CURRENT ( A) 380 240 120 110 IREF vs TEMPERATURE 335 NO CLOCK, 5V CLOCKING, 5V NO CLOCK, 3.3V CLOCKING, 3.3V 290 245 1.8 2.4 3.0 3.6 200 -50 4.2 -10 70 TEMPERATURE °C Figure 18. Figure 19.
PAGE 13
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 5V Glitch Response 1.275 Mid Scale-1 to Mid Scale OUTPUT VOLTAGE (V) 1.270 1.265 1.260 1.255 1.250 1.245 1.240 2,000 2,500 3,000 3,500 4,000 TIME (ns) Figure 22.
PAGE 14
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 www.ti.com FUNCTIONAL DESCRIPTION DAC ARCHITECTURE OVERVIEW The DAC161S055 uses a resistor array to convert the input code to an analog signal, which in turn is buffered by the rail-to-rail output amplifier. The resistor array is factory trimmed to achieve 16-bit accuracy. An SPI interface shifts the input codes into the device. The acquired input code is stored in the PREREG register.
PAGE 15
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 The acquired data is shifted into an internal 24 bit shift register (MSB first) which is configured as a 24 bit deep FIFO. As the data is being shifted into the FIFO via the SDI pin, the prior contents of the register are being shifted out through the SDO output. While CSB is high, SDO is in a high-Z state. At the falling edge of CSB, SDO presents the MSB of the data present in the shift register.
PAGE 16
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 www.ti.com SYNC CLK (1) (2) (3) SPI/QSPI MICROWIRE CSB CSB CSB MASTER SCLK SCLK SCLK SDI MOSI SDO DAC161S055 SDI SDO SDI DAC161S055 SDO DAC161S055 MISO A sample of SPI data transfer appropriate for a 3 DAC Daisy Chain is shown in the figure below. 72 Clock Cycles SYNC MOSI DATA (3) DATA (2) DATA (1) POWER-UP DEFAULT OUTPUT It is possible to power up the DAC with the output either at GND or midscale.
PAGE 17
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 CSB SCLK 2 1 3 4 23 24 LDACB LDACB must not transition here (may be held low for whole transaction) The DAC Configuration command LDAC (see Section INSTRUCTION SET below) will also update the DAC output as soon as it is received. The effect of hardware LDACB or software LDAC is the same i.e. data is transferred from the PREREG to DACREG and output of the DAC is updated.
PAGE 18
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 www.ti.com INTERNAL REGISTERS There are 3 registers that are accessible to the user. The data registers (PREREG and DACREG) are both readable and writable from the command set. The CONFIG register is only readable from the command set. Bits in the CONFIG register are set by the commands detailed in Section INSTRUCTION SET.
PAGE 19
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 INSTRUCTION SET The instruction set for the DAC161S055 is common to the family of single and multi channel devices (DAC16xS055). The DAC161S055 has only a single channel — Channel 0. NOTE DATA WRITING and REGISTER READING instructions encode the channel address as a binary triplet (A2,A1,A0) as the last three LSBs of the command byte. DAC CONFIGURATION instructions encode the channel selection by a bit set in the data bytes.
PAGE 20
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 MNEMONIC www.ti.com Command Byte[7:0] DATA[15:8] RDCO 1 0 0 1 0 A2 A1 A0 0000 0000 RDIN 1 0 0 1 1 A2 A1 A0 DACDATA[15:8] 20 DATA [7:0] Description 0000 0,swb,sel_10k, sel_hiz Read CONFIG register. DACDATA[7:0] Read DACREG register.
PAGE 21
DAC161S055 www.ti.com SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 APPLICATIONS INFORMATION SAMPLE INSTRUCTION SEQUENCE The following table shows an example instruction sequence to illustrate the usage of different modes of operation of the DAC. This sequence is for a one channel DAC. Step Instruction 8-bit Command 16 bit Payload Comments 1 CLR 0000 0001 0000 0000 0000 0000 Clear device - return to Power-Up Default State 2 WR 0000 1000 0100 0000 0000 0000 Write 1/4 FS into channel 0.
PAGE 22
DAC161S055 SNAS503B – NOVEMBER 2010 – REVISED JANUARY 2012 www.ti.com LAYOUT, GROUNDING AND BYPASSING For best accuracy and minimum noise, the printed circuit board containing the DAC should have separate analog and digital areas. These areas are defined by the locations of the analog and digital power planes. Both power planes should be in the same board layer. There should be a single ground plane.
PAGE 23
PACKAGE OPTION ADDENDUM www.ti.
PAGE 24
PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DAC161S055CISQ/NOPB WQFN SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant RGH 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 DAC161S055CISQE/NOP B WQFN RGH 16 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 DAC161S055CISQX/NOP B WQFN RGH 16 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.
PAGE 25
PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC161S055CISQ/NOPB WQFN RGH 16 1000 213.0 191.0 55.0 DAC161S055CISQE/NOP B WQFN RGH 16 250 213.0 191.0 55.0 DAC161S055CISQX/NOP B WQFN RGH 16 4500 367.0 367.0 35.
PAGE 26
MECHANICAL DATA RGH0016A SQA16A (Rev A) www.ti.
PAGE 27
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.