Datasheet

t
PD
t
H
t
LPW
t
CPW
t
SET
D[13:0]
(n)
D[13:0]
(n + 1)
t
S
I
OUT
(n)
I
OUT
(n + 1)
50%
DATAIN
WRT1
WRT2
CLK1
CLK2
I 1
OUT
I 2
OUT
DAC2904
www.ti.com .............................................................................................................................................. SBAS198C –AUGUST 2001–REVISED OCTOBER 2009
TIMING REQUIREMENTS
PARAMETER MIN TYP MAX UNIT
t
S
Input setup time 2 ns
t
H
Input hold time 1.5 ns
t
LPW
, t
CPW
Latch/Clock pulse width 3.5 4 ns
t
CW
Delay rising CLK edge to rising WRT edge 0 t
PW
– 2 ns
t
PD
Propagation delay 1 ns
t
SET
Settling time (0.1%) 30 ns
DIGITAL INPUTS AND TIMING
The data input ports of the DAC2904 accept a standard positive coding with data bit D13 being the most
significant bit (MSB). The converter outputs support a clock rate of up to 125MSPS. The best performance will
typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long
as the timing specifications are met. Also, the set-up and hold times may be chosen within their specified limits.
All digital inputs of the DAC2904 are CMOS compatible. The logic thresholds depend on the applied digital
supply voltages, such that they are set to approximately half the supply voltage; V
th
= +V
D
/2 (±20% tolerance).
The DAC2904 is designed to operate with a digital supply (+V
D
) of +3.0V to +5.5V.
The two converter channels within the DAC2904 consist of two independent, 14-bit, parallel data ports. Each
DAC channel is controlled by its own set of write (WRT1, WRT2) and clock (CLK1, CLK2) inputs. Here, the WRT
lines control the channel input latches and the CLK lines control the DAC latches. The data is first loaded into the
input latch by a rising edge of the WRT line. This data is presented to the DAC latch on the following falling edge
of the WRT signal. On the next rising edge of the CLK line, the DAC is updated with the new data and the analog
output signal will change accordingly. The double latch architecture of the DAC2904 results in a defined
sequence for the WRT and CLK signals, expressed by parameter t
CW
. A correct timing is observed when the
rising edge of CLK occurs at the same time, or before, the rising edge of the WRT signal. This condition can
simply be met by connecting the WRT and CLK lines together. Note that all specifications were measured with
the WRT and CLK lines connected together.
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