Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VQFN 48

1.2-V

Reference

DACA

DACB

Clock Distribution

BIASJ

IOUTAP

IOUTAN

IOUTBP

IOUTBN

DACCLKP

DACCLKN

D11P

D11N

D0P

D0N

AVDD33

LVPECL

LVDS

VREF

De-interleave

12/10

SLEEPB

GND

ATEST

VFUSE

DVDD18

CLKVDD18

100

DAC3152

DAC3162

www.ti.com

SLAS736D –NOVEMBER 2010–REVISED AUGUST 2012

Dual-Channel, 10-/12-Bit, 500-MSPS Digital-to-Analog Converters (DACs)

Check for Samples: DAC3152, DAC3162

FEATURES

DESCRIPTION

The DAC3152/DAC3162 is a low-power, low-latency,

• Low Power: 270 mW at 500 MSPS

high-dynamic-range, dual-channel, 10-/12-bit, pin-

• LVDS Input Data Bus

compatible family of digital-to-analog converters

– Interleaved DDR Data Load

(DACs) with a sample rate as high as 500 MSPS.

• High DC Accuracy: ±0.25 LSB DNL (10-bit),

The device simplicity (no software required), low

± 0.5 LSB INL (12-bit)

latency, and low power simplify the design of complex

systems. The DACs interface seamlessly with the

• Low Latency: 1.5 Clock Cycles

high-performance TRF370333 analog quadrature

• Simple Control: No Software Required

modulator for direct upconversion architectures.

• Differential Scalable Output: 2 mA to 20 mA

Digital data for both DAC channels is interleaved

• On-Chip 1.2-V Reference

through a single LVDS data bus with on-chip

• 1.8-V and 3.3-V DC Supplies

termination. The high input rate of the devices allows

the processing of wide-bandwidth signals.

• Space Saving Package: 48-pin 7-mm × 7-mm

QFN

The devices are characterized for operation over the

entire industrial temperature range of –40°C to 85°C

APPLICATIONS

and are available in a small 48-pin 7-mm × 7-mm

QFN package.

• Cellular Base Stations

• Wideband Communications The low power, small size, speed, superior crosstalk,

simplicity, and low latency of the DAC3152/DAC3162

• Medical Instrumentation

make them an attractive fit for a variety of

• Test and Measurement

applications.

FUNCTIONAL BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 Dual-Channel, 10-/12-Bit, 500-MSPS Digital-to-Analog Converters (DACs) Check for Samples: DAC3152, DAC3162 FEATURES DESCRIPTION • • The DAC3152/DAC3162 is a low-power, low-latency, high-dynamic-range, dual-channel, 10-/12-bit, pincompatible family of digital-to-analog converters (DACs) with a sample rate as high as 500 MSPS.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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DAC3152 DAC3162 www.ti.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE MAX –0.5 2.3 V –0.5 2.3 V AVDD33 –0.5 4 V D[11..0]P/N –0.5 DVDD18 + 0.5 V DACCLKP/N –0.5 CLKVDD18 + 0.5 V V BIASJ, SLEEPB –0.5 AVDD33 + 0.7 V V –1 DVDD18, CLKVDD18 Supply-voltage range (2) VFUSE Pin-voltage range (2) UNIT MIN AVDD33 + 0.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS – DC SPECIFICATION DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.3 V, fDAC = 500 MSPS, fOUT = 1 MHz over recommended operating free-air temperature range, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS Resolution DAC3152 MIN TYP DAC3162 MAX 10 MIN TYP UNIT MAX 12 Bits DC ACCURACY DNL Differential nonlinearity INL Integral nonlinearity ±0.1 ±0.4 LSB ±0.15 ±0.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.3 V, fDAC = 500 MSPS, fOUT = 1 MHz over recommended operating free-air temperature range, IOUTFS = 20mA (unless otherwise noted) PARAMETER ANALOG OUTPUT fDAC TEST CONDITIONS TYP DAC3162 MAX MIN TYP UNIT MAX (1) Maximum DAC rate ts(DAC) Output settling time to 0.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com Typical Characteristics DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.3 V, fDAC = 500 MSPS, fOUT = 1 MHz, IOUTfs = 20 mA (unless otherwise noted) 100 Channel A Channel B Third Harmonic Distortion (dBc) Second Harmonic Distortion (dBc) 90 80 70 60 70 60 50 0 50 fDAC = 500 MSPS 100 150 Output Frequency (MHz) 200 40 250 0 50 G001 Figure 1.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 Typical Characteristics (continued) DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com Typical Characteristics (continued) DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 Typical Characteristics (continued) DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.3 V, fDAC = 500 MSPS, fOUT = 1 MHz, IOUTfs = 20 mA (unless otherwise noted) 100 −120 Channel A Channel B 90 −130 NSD (dBc/Hz) IMD3 (dBc) Channel A Channel B −125 80 70 −135 −140 −145 −150 60 −155 fDAC = 500 MSPS 50 0 50 Output Frequency (MHz) −160 100 Figure 19.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com Typical Characteristics (continued) DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.3 V, fDAC = 500 MSPS, fOUT = 1 MHz, IOUTfs = 20 mA (unless otherwise noted) −20 −20 W-CDMA Test Model 1 at 30 MHz −40 fOUT = 30 MHz fDAC = 491.52 MSPS −40 fOUT = 70 MHz fDAC = 491.52 MSPS −50 −60 −70 ACPR = 68.4 dBc ALT1 = 68.7 dBc −80 Power (dBm) −50 Power (dBm) W-CDMA Test Model 1 at 70 MHz −30 −30 −60 −70 ACPR = 66.9 dBc ALT1 = 67.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 Typical Characteristics (continued) DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.3 V, fDAC = 500 MSPS, fOUT = 1 MHz, IOUTfs = 20 mA (unless otherwise noted) 300 dac3162 dac3152 Total Power (mW) 270 240 210 180 150 0 100 200 300 400 FDAC Frequency (MSPS) 500 600 G000 Figure 31.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com APPLICATION INFORMATION DATA INTERFACE The parallel-port data interface to the device consists of a single LVDS bus that accepts interleaved A and B data with up to 12-bit resolution. Data is sampled by the LVPECL double-data-rate (DDR) clock DACCLK. DACCLK is additionally used for the data conversion process, and hence a low-jitter source is recommended. Setup and hold requirements must be met for proper sampling.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 CLOCK INPUT The DAC clock (DACCLKP/N) is an internally biased differential input that for optimal performance should be driven by a low-jitter clock source. The DACCLK signal is used for both data latching (in DDR format) and as the data conversion clock. Figure 33 shows an equivalent circuit for the DAC input clock. CLKVDD 500 Ω DACCLKP Note: Input common mode level is approximately 1/2 ´ CLKVDD18, or 0.9 V nominal.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com A single-ended clock, such as a clean sinusoid or a 1.8 V LVCMOS signal (for low-rate operation), can also be used to drive the clock if configured as in the input circuits of Figure 36 and Figure 37. CAC 0.1 µF 1:4 DACCLKP RT 200 Ω Optional, may be bypassed for sine-wave input DACLCKN Figure 36. Clock Input Configuration Using 50-Ω Cable Input TTL/CMOS source Ropt 22 Ω CAC 0.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 DATA INPUTS The input data LVDS pairs (D[11:0]P/N) have the input configuration shown in Figure 38. Figure 39 shows the typical input levels and common-mode voltage used to drive these inputs. DVDD18 100 Ω LVDS Receiver internal digital in GND Figure 38. D[13:0]P/N LVDS Input Configuration Example DAC LVDS Receiver 100 VA,B VA 1.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com REFERENCE OPERATION The DAC3152/DAC3162 uses a band-gap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS through resistor RBIAS is defined by the on-chip band-gap reference voltage and control amplifier.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 ANALOG CURRENT OUTPUTS The DAC outputs can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF transformer. Figure 41 and Figure 42 show the 50-Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratios, respectively. Note that the center tap of the primary input of the transformer must be connected to AVDD to enable a dc current flow.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com PASSIVE INTERFACE TO ANALOG QUADRATURE MODULATORS A common application in communication systems is to interface the DAC to an IQ modulator like the TRF3703 family of modulators from Texas Instruments. The input of the modulator is generally of high impedance and requires a specific common-mode voltage.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 V1 R1 I I R3 DAC3152/ DAC3162 TRF370333 V2 R3 I I R1 V1 Figure 45. DAC3152/DAC3162 to TRF370333 Interface In most applications, a baseband filter is required between the DAC and the modulator to eliminate the DAC images. This filter can be placed after the common-mode biasing network. For the DAC-to-modulator network shown in Figure 46, R2 and the filter load R4 must be considered into the DAC impedance.
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DAC3152 DAC3162 SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 www.ti.com POWER-UP SEQUENCE The following start-up sequence is recommended to power up the DAC3152/DAC3162: • Supply 1.8 V to DVDD18 and CLKVDD18 simultaneously, and 3.3 V to AVDD33. Within AVDD33, the multiple AVDD33 pins should be powered up simultaneously. The 1.8-V and 3.3-V supplies can be powered up simultaneously or in any order. There are no specific requirements on the ramp rate for the supplies.
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DAC3152 DAC3162 www.ti.com SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012 REVISION HISTORY Changes from Original (November 2010) to Revision A • Page Deleted the DAC3172 device ............................................................................................................................................... 1 Changes from Revision A (November 2010) to Revision B Page • Changed Feature bullet From: High DC Accuracy: ±1 LSB DNL, ±2 LSB INL To: High DC Accuracy: ±0.25 LSB DNL (10-bit), ± 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DAC3152IRGZR VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 DAC3152IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 DAC3162IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC3152IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 DAC3152IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 DAC3162IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 DAC3162IRGZT VQFN RGZ 48 250 336.6 336.6 28.
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