Datasheet

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DAC3484

www.ti.com

SLAS749C –MARCH 2011–REVISED AUGUST 2012

Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

Check for Samples: DAC3484

FEATURES

DESCRIPTION

The DAC3484 is a very low power, high dynamic

• Very Low Power: 1.27 W at 1.25 GSPS, Full

range, quad-channel, 16-bit digital-to-analog

Operating Conditions

converter (DAC) with a sample rate as high as 1.25

• Multi-DAC Synchronization

GSPS.

• Selectable 2x, 4x, 8x, 16x Interpolation Filter

The device includes features that simplify the design

– Stop-Band Attenuation > 90 dBc

of complex transmit architectures: 2x to 16x digital

interpolation filters with over 90 dB of stop-band

• Flexible On-chip Complex Mixing

attenuation simplify the data interface and

– Two Independent Fine Mixers with 32-bit

reconstruction filters. Independent complex mixers

NCOs

allow flexible carrier placement. A high-performance

– Power Saving Coarse Mixers: ± n×Fs/8

low jitter clock multiplier simplifies clocking of the

device without significant impact on the dynamic

• High Performance, Low Jitter Clock

range. The digital Quadrature Modulator Correction

Multiplying PLL

(QMC) enables complete IQ compensation for gain,

• Digital I and Q Correction

offset, phase and group delay between channels in

– Gain, Phase, Offset, and Group Delay

direct up-conversion applications.

Correction

Digital data is input to the device through a 16-bit

• Digital Inverse Sinc Filter

LVDS data bus with on-chip termination. The device

• Flexible 16-Bit LVDS Input Data Bus

includes a FIFO, data pattern checker and parity test

to ease the input interface. The interface also allows

– 8 Sample Input FIFO

full synchronization of multiple devices.

– Data Pattern Checker

The device is characterized for operation over the

– Parity Check

entire industrial temperature range of –40°C to 85°C

– GC5330 Compatible

and is available in a very-small 88-pin 9x9mm WQFN

• Temperature Sensor

package.

• Differential Scalable Output: 10mA to 30mA

The DAC3484 very low power, small size, superior

• Multiple Package Options: 88-pin 9x9mm crosstalk, high dynamic range and features are an

ideal fit for systems with multiple transmit channels.

WQFN and 196-ball 12mmx12mm BGA

(GREEN / Pb-Free)

APPLICATIONS

• Cellular Base Stations

• Diversity Transmit

• Wideband Communications

spacing

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (89 pages)

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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC) Check for Samples: DAC3484 FEATURES DESCRIPTION • The DAC3484 is a very low power, high dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS. 1 • • • • • • • • • • Very Low Power: 1.27 W at 1.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com PIN FUNCTIONS (continued) PIN NAME NO. I/O DESCRIPTION LVDS positive input data bits 0 through 15. Internal 100 Ω termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR). A7, A8, B9, B10, A12, A13, A14, A15, B17, B18, B19, B20, A23, A24, B23, B24 I D[15..0]N B7, B8, A10, A11, B11, B12, B13, B14, A19, A20, A21, A22, B21, B22, A26, A27 I LVDS negative input data bits 0 through 15.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 PIN FUNCTIONS (continued) PIN NAME NO. I/O DESCRIPTION SCLK A31 I Serial interface clock. Internal pull-down. SDENB B28 I Active low serial data enable, always an input to the DAC3484. Internal pull-up. SDIO A30 I/O Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional 4-pin mode. Internal pull-down. SDO B27 O Uni-directional serial interface data in 4-pin mode.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 PIN FUNCTIONS PIN NAME NO. I/O DESCRIPTION AVDD D10, E11, F11, G11, H11, J11, K11, L10 I Analog supply voltage. (3.3 V) ALARM N12 O CMOS output for ALARM condition. The ALARM output functionality is defined through the config7 register. Default polarity is active low, but can be changed to active high via config0 alarm_out_pol control bit. BIASJ H12 O Full-scale output current bias. For 30mA full-scale output current, connect 1.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com PIN FUNCTIONS (continued) PIN NAME NO. I/O DESCRIPTION GND A10, A13, A14, B10, B11, B12, B13, C5, C6, C7, C8, C9, C10, C13, D8, D13, D14, E8, E12, E13, F6, F7, F8, F9, F12, F13, G6, G7, G8, G9, G13, G14, H6, H7, H8, H9, H13, H14, J6, J7, J8, J9, J12, J13, K8, K13, L8, L13, L14, M5, M6, M7, M8, M9, M10, M11, M12, M13, N13, P13, P14 I These pins are ground for all supplies. IOUTAP B14 O A-Channel DAC current output.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 PIN FUNCTIONS (continued) PIN NAME I/O NO. DESCRIPTION TXENABLE N9 I Transmit enable active high input. Internal pull-down. To enable analog output data transmission, set sif_txenable in register config3 to “1” or pull CMOS TXENABLE pin to high. To disable analog output, set sif_txenable to “0” and pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. TESTMODE A8 O This pin is used for factory testing.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com THERMAL INFORMATION DAC3484 THERMAL METRIC (1) RKD PACKAGE ZAY PACKAGE 88 PINS 196 BALL 22.1 37.6 (2) θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance (3) 7.1 6.8 θJCbot Junction-to-case (bottom) thermal resistance (4) 0.6 N/A θJB Junction-to-board thermal resistance (5) 4.7 16.8 ψJT Junction-to-top characterization parameter (6) 0.1 0.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (1) over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted) PARAMETER TEST CONDITIONS Resolution MIN TYP MAX UNIT 16 Bits DC ACCURACY DNL Differential nonlinearity INL Integral nonlinearity 1 LSB = IOUTFS/216 ±2 LSB ±4 LSB ANALOG OUTPUT Coarse gain linearity Offset error Gain error Gain mismatch ±0.04 LSB ±0.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS(1) (continued) over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted) PARAMETER POWER SUPPLY PSRR TEST CONDITIONS MIN TYP MAX UNIT (3) AVDD, IOVDD, PLLAVDD All Conditions 3.14 3.3 3.46 V DIGVDD All Conditions 1.14 1.2 1.32 V CLKVDD, DACVDD FDAC Sampling Rate ≤ 1.25GSPS, PLL OFF FDAC Sampling Rate ≤ 1GSPS, PLL ON 1.14 1.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INPUTS: D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, PARITYP/N (1) VA,B+ Logic high differential input voltage threshold VA,B– Logic low differential input voltage threshold VCOM Input Common Mode 1.0 1.2 1.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted) PARAMETER TEST CONDITIONS / COMMENTS MIN TYP MAX UNIT ANALOG OUTPUT (1) fDAC Maximum DAC rate ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF tpd Output propagation delay DAC outputs are updated on the falling edge of DAC clock.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer (unless otherwise noted) 100 10 PLL Enabled w/ PFD of 78.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer (unless otherwise noted) 4x Interpolation, 0 dBFS fDAC = 1228.8 MSPS fOUT = 120 MHz 4x Interpolation, 0 dBFS fDAC = 1228.8 MSPS fOUT = 200 MHz G031 Figure 31.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 4x interpolation, NCO enabled, Mixer Gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer (unless otherwise noted) 100 BGA MrQFN 90 IMD3 (dBc) 80 70 60 50 40 30 0 100 200 300 400 Output Frequency (dB) 500 600 G049 Figure 49.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com DEFINITION OF SPECIFICATIONS Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a 3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio. Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 R/W Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from DAC3484 and a low indicates a write operation to DAC3484. [A6 : A0] Identifies the address of the register to be accessed during the read or write operation.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Figure 50 shows the serial interface timing diagram for a DAC3484 write operation. SCLK is the serial interface clock input to DAC3484. Serial data enable SDENB is an active low input to DAC3484. SDIO is serial data in. Input data to DAC3484 is clocked on the rising edges of SCLK.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Figure 51 shows the serial interface timing diagram for a DAC3484 read operation. SCLK is the serial interface clock input to DAC3484. Serial data enable SDENB is an active low input to DAC3484. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out from the DAC3484 during the data transfer cycle, while SDO is in a high-impedance state.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Table 2.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Table 2.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com REGISTER DESCRIPTIONS Register name: config0 – Address: 0x00, Default: 0x049C Register Name Address Bit Name Function config0 0x00 15 qmc_offsetAB_ena When set, the digital Quadrature Modulator Correction (QMC) offset correction for the AB data path is enabled. 0 14 qmc_offsetCD_ena When set, the digital Quadrature Modulator Correction (QMC) offset correction for the CD data path is enabled.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Register name: config1 – Address: 0x01, Default: 0x050E Register Name Address Bit config1 0x01 15 iotest_ena When set, enables the data pattern checker test. The outputs are deactivated regardless of the state of TXENABLE and sif_txenable. 0 14 Reserved Reserved for factory use. 0 13 Reserved Reserved for factory use.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Register name: config2 – Address: 0x02, Default: 0x7000 Register Name Address Bit config2 0x02 15 16bit_in When set, the input interface is set to word-wide mode. When cleared, the input interface is set to byte-wide mode. 0 14 dacclkgone_ena When set, the DACCLK-gone signal from the clock monitor circuit can be used to shut off the DAC outputs.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Register name: config5 – Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO CLEAR) Register Name Address config5 0x05 Bit Name Function Default Value 15 alarm_from_zerochk This alarm indicates the 8-bit FIFO write pointer address has an all zeros patterns. Due to pointer address being a shift register, this is not a valid address and will cause the write pointer to be stuck until the next sync.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Register name: config7 – Address: 0x07, Default: 0xFFFF Register Name Address Bit config7 0x07 15:0 Name alarms_mask(15:0) Default Value Function These bits control the masking of the alarms.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Register name: config11 – Address: 0x0B, Default: 0x0000 Register Name Address Bit config10 0x0A 15 Reserved Reserved for factory use. 0 14 Reserved Reserved for factory use. 0 13 Reserved Reserved for factory use. qmc_offsetD(12:0) DACD offset correction. The offset is measured in DAC LSBs.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Register name: config16 – Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC) Register Name Address Bit config16 0x10 15 Reserved Reserved for factory use. 0 14 Reserved Reserved for factory use. 0 13:12 dual_ena (1:0) To enable the dual channel mode, set Config1, bit <8> to "0" and Config16, bit<13:12> to "11". This dual channel mode is functionally equivalent to the dual channel DAC3482 (channels B and C active).
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Register name: config20 – Address: 0x14, Default: 0x0000 Register Name Address Bit config20 0x14 15:0 Name phase_ addAB(15:0) Default Value Function The phase_addAB(15:0) value is used to determine the NCO frequency. The two’s complement formatted value can be positive or negative. Each LSB represents Fs/(2^32) frequency step.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Register name: config25 – Address: 0x19, Default: 0x0440 Register Name Address Bit config25 0x19 15:8 pll_m(7:0) M portion of the M/N divider of the PLL. If pll_m<7> = 0, the M divider value has the range of pll_m<6:0>, spanning from 4 to 127. (i.e. 0, 1, 2, and 3 are not valid.) If pll_m<7> = 1, the M divider value has the range of 2 × pll_m<6:0>, spanning from 8 to 254. (i.e. 0, 2, 4, and 6 are not valid.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Register name: config27 – Address: 0x1B, Default: 0x0000 Register Name Address Bit config27 0x1B 15 extref_ena Allows the device to use an external reference or the internal reference. MM 0: Internal reference MM 1: External reference 0 14 Reserved Reserved for factory use. 0 13 Reserved Reserved for factory use. 0 12 Reserved Reserved for factory use. 0 11 fuse_sleep Put the fuses to sleep when set high.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Register name: config30 – Address: 0x1E, Default: 0x1111 Register Name Address Bit config30 0x1E 15:12 syncsel_qmoffsetAB(3:0) Selects the syncing source(s) of the AB data path double buffered QMC offset registers. A ‘1’ in the bit enables the signal as a sync source. More than one sync source is permitted.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Register name: config32 – Address: 0x20, Default: 0x2400 Register Name Address Bit config32 0x20 15:12 syncsel_fifoin(3:0) Selects the syncing source(s) of the FIFO input side. A ‘1’ in the bit enables the signal as a sync source. More than one sync source is permitted.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Register name: config35 – Address: 0x23, Default: 0xFFFF Register Name Address Bit config35 0x23 15:0 Name sleep_cntl(15:0) Default Value Function Controls the routing of the CMOS SLEEP signal (pin B40) to different blocks. When a bit in this register is set, the SLEEP signal will be sent to the corresponding block. The block will only be disabled when the SLEEP is logic HIGH and the correspond bit is set to “1”.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Register name: config41 – Address: 0x29, Default: 0x1A1A Register Name Address Bit Name config41 0x29 15:0 iotest_pattern4 Default Value Function Dataword4 in the IO test pattern. It is used with the seven other words to test the input data. 0x1A1A Register name: config42 – Address: 0x2A, Default: 0x1616 Register Name Address Bit config42 0x2A 15:0 Name iotest_pattern5 Default Value Function Dataword5 in the IO test pattern.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Register name: config48 – Address: 0x30, Default: 0x0000 Register Name Address Bit config48 0x30 15:0 Name sifdac(15:0) Function Value sent to the DACs when sifdac_ena is asserted. DATACLK must be running to latch this value into the DACs. The format would be based on twos in register config2.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 DATA INTERFACE The DAC3484 has a 16-bit LVDS bus that accepts quad, 16-bit data either in word-wide or dual byte-wide formats. The quad, 16-bit data can be input to the device using either a single-bus, 16-bit interface or a dual-bus, 8-bit interface. The selection between the two modes is done through 16bit_in in the config2 register. The LVDS bus inputs in each mode are shown in Table 3. Table 3.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com BYTE-WIDE FORMAT The dual-bus, 8-bit interface is selected by setting 16bit_in to “0” in the config2 register. In this mode the 16-bit data for channels A and B is interleaved in the form A0[15:8], A0[7:0], B0[15:8], B0[7:0], A1[15:8]… into the D[15:8]P/N LVDS inputs. Similarly data for channels C and D is interleaved into the D[7:0]P/N LVDS inputs.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Clock Handoff Initial Position D[15:0] B-Data, 16-Bit Frame Align C-Data, 16-Bit D-Data, 16-Bit 0 ...
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Table 4. FIFO Operation Modes config0 and config32 FIFO Bits FIFO Mode Dual Sync Sources fifo_ena syncsel_fifoout Bit 3: sif_sync Bit 2: OSTR Bit 1: FRAME 0 1 0 0 1 or 0 Depends on the sync source X 1 Bit 0: SYNC Single Sync Source 1 0 0 1 or 0 Depends on the sync source Bypass 0 X X X DUAL SYNC SOURCES MODE This is the recommended mode of operation for those applications that require precise control of the output timing.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com PLL BYPASS MODE In PLL bypass mode a very high quality clock is sourced to the DACCLK inputs. This clock is used to directly clock the DAC3484 DAC sample rate clock. This mode gives the device best performance and is recommended for extremely demanding applications. The bypass mode is selected by setting the following: 1. pll_ena bit in register config24 to “0” to bypass the PLL circuitry. 2.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 4000 Coarse-Tuning Bits @ VCO Frequency (MHz) 3900 VCO Frequency (MHz ) - 3253 11.6 3800 3700 3600 3500 3400 3300 0 8 16 32 24 40 48 56 64 Coarse-Tuning Bits Figure 58. Typical PLL/VCO Lock Range vs Coarse Tuning Bits Common wireless infrastructure frequencies (614.4MHz, 737.28MHz, 1.2288GHz, etc.) are generated from this VCO frequency in conjunction with the pre-scaler setting as shown in Table 5. Table 5.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com LPF R = 1 kΩ C2 = 1 nF C1 = 100 nF S0514-01 Figure 59. Recommended External Loop Filter The PLL generates an internal OSTR signal and does not require the external LVPECL OSTR signal. The OSTR signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same as the PFD frequency. Therefore, using PLL with Dual Sync Sources mode would require the PFD frequency to be the pre-defined OSTR frequency.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the DACCLK.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Both SYNC and DACCLK can be set as low frequency signals to greatly simplifying trace routing (SYNC can be just a pulse as a single rising edge is required, if using a periodic signal it is recommended to clear the pll_ndivsync_ena bit after resetting the PLL dividers).
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 DACCLKP/N D[15:0]P/N FPGA DAC3484 DAC1 FRAMEP/N Clock Generator PLL/ DLL LVDS Interface LVPECL Outputs Delay 1 DATACLKP/N Variable delays due to variations in the FPGA(s) output paths or board level wiring or temperature/voltage deltas 0 to 2 DAC Clock Cycles D[15:0]P/N LVPECL Outputs FRAMEP/N DATACLKP/N Delay 2 DAC3484 DAC2 DACCLKP/N B0456-03 Figure 63.
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DAC3484 www.ti.com 20 20 0 0 –20 –20 –40 –40 Magnitude (dB) Magnitude (dB) SLAS749C – MARCH 2011 – REVISED AUGUST 2012 –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 –160 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 f/fIN 0.5 0.6 0.7 0.8 0.9 f/fIN G049 Figure 64. Magnitude Spectrum for FIR0 SPACER Figure 65.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 20 20 0 0 –20 –20 –40 –40 Magnitude (dB) Magnitude (dB) www.ti.com –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 –160 –160 0 0.5 1 1.5 2 2.5 3 3.5 4 0 1 2 3 f/fDATA 4 5 6 7 8 f/fDATA G054 G055 Figure 70. 8x Interpolation Composite Response SPACER Figure 71. 16x Interpolation Composite Response SPACER 4 3 FIR4 Magnitude (dB) 2 1 Corrected 0 –1 –2 sin(x)/x –3 –4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Table 7.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 COMPLEX SIGNAL MIXER The DAC3484 has two paths of complex signal mixer blocks that contain two full complex mixer (FMIX) blocks and power saving coarse mixer (CMIX) blocks. The signal path is shown in Figure 73.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com With the complex mixer enabled, the two channels in the mixer path are treated as complex vectors of the form IIN(t) + j QIN(t). The complex signal multiplier (shown in Figure 75) will multiply the complex channels with the sine and cosine terms generated by the NCO.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Table 8. Fs/2, Fs/4, and –Fs/4 Mixing Sequence (continued) MODE MIXING SEQUENCE Iout = {+I1, -I2, +I3, -I4…} fs/2 Qout = {+Q1, -Q2, +Q3, -Q4…} Iout = {+I1, -Q2, -I3, +Q4…} fs/4 Qout = {+Q1, +I2, -Q3, -I4…} Iout = {+I1, +Q2, -I3, -Q4…} -fs/4 Qout = {+Q1, -I2, -Q3, +I4…} The fs/8 mixer can be enabled along with various combinations of fs/2, fs/4, and –fs/4 mixer.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com REAL CHANNEL UPCONVERSION The mixer in the DAC34H84 treats the A, B, C, and D inputs are complex input data and produces a complex output for most mixing frequencies. The real input data for each channel can be isolated only when the mixing frequency is set to normal mode or fs/2 mode. Refer to Table 8 for details.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 qmc_gainA[10:0] 11 16 Σ I Data In (A) 16 I Data Out (A) 12 qmc_phaseAB[11:0] 16 16 Q Data In (B) Q Data Out (B) 11 qmc_gainB[10:0] qmc_gainC[10:0] 11 16 Σ I Data In (C) 16 I Data Out (C) 12 qmc_phaseCD[11:0] 16 16 Q Data In (D) Q Data Out (D) 11 qmc_gainD[10:0] B0164-03 Figure 77.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com qmc_offsetA {–4096, –4095, ..., 4095} 13 16 A Data In 16 B Data In 16 Σ A Data Out 16 Σ B Data Out 13 qmc_offsetB {–4096, –4095, ..., 4095} qmc_offsetC {–4096, –4095, ..., 4095} 13 16 C Data In 16 D Data In 16 Σ C Data Out 16 Σ D Data Out 13 qmc_offsetD {–4096, –4095, ..., 4095} B0165-03 Figure 78.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled (tsense_sleep = “0” in register config26) a conversion takes place each time the serial port is written or read. The data is only read and sent out by the digital block when the temperature sensor is read in tempdata(7:0) in config6.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com The alarms can be cleared by writing 0x0000 to iotest_results(15:0) and “0” to alarm_from_iotest through the serial interface. The serial interface will read back 0s if there are no errors or if the errors are cleared. The corresponding alarm bit will remain a “1” if the errors remain.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 16-Bit 0 Pattern 0 Bit-by-Bit Compare 0 1 Pattern 1 Bit-by-Bit Compare 1 FRAME or SYNC 16-Bit LVDS Drivers Only one Data Format edge needed Pattern 0 ...
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com PARITY CHECK TEST The DAC3484 has a parity check test that enables continuous validity monitoring of the data received by the DAC. Parity check testing in combination with the data pattern checker offer an excellent solution for detecting board assembly issues due to missing pad connections. For the parity check test, an extra parity bit is added to the data bits to ensure that the total number of set bits (bits with value 1) is even or odd.
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DAC3484 www.ti.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Parity alarms • alarm_rparity. Occurs when there is a parity error in the data captured by the rising edge of DATACLKP/N. The PARITYP/N input is the parity bit (word-by-word parity test). • alarm_fparity. Occurs when there is a parity error in the data captured by the falling edge of DATACLKP/N. The PARITYP/N input is the parity bit (word-by-word parity test). • alarm_frame_parity_err.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 (b) For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used. (c) For multi-DAC synchronization in PLL mode, the LVDS SYNCP/N signal is used to sync the PLL Ndivider and can be sourced from either the FPGA/ASIC pattern generator or clock distribution circuit as long as the t(SYNC_PLL) setup and hold timing requirement is met with respect to the reference clock source at DACCLKP/N pins.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com freq = fNCO x 2^32 / 1228.8 = 429496730 = 0x1999999A phaseaddAB(31:0) or phaseaddCD(31:0) = 0x19999999A NCO SYNC = sif_sync EXAMPLE START-UP SEQUENCE Table 10.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Table 10. Example Start-Up Sequence Description (continued) STEP READ/WRITE ADDRESS VALUE DESCRIPTION 32 Write 0x20 0x2400 FIFO Input Pointer Sync Source = ISTR FIFO Output Pointer Sync Source = OSTR (from PLL N-divider output) Clock Divider Sync Source = OSTR 33 N/A N/A N/A Provide all the LVDS DATA and DATACLK Provide rising edge FRAMEP/N and rising edge SYNCP/N to sync the FIFO input pointer and PLL Ndividers.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com Figure 84 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential ECL/PECL source. CAC 0.1 μF Differential ECL or (LV)PECL Source + CLKIN CAC 0.1 μF 100 Ω CLKINC – RT 150 Ω RT 150 Ω S0029-02 Figure 84.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 Example DAC3484 VA, B VCOM = (VA + VB)/2 VA 1.4 V VB 1V LVDS Receiver 100 Ω 400 mV VA, B VA 0V –400 mV VB GND 1 Logical Bit Equivalent 0 B0459-03 Figure 86. LVDS Data Input Levels Table 11. Example LVDS Data Input Levels Applied Voltages Resulting Differential Voltage Resulting Common-Mode Voltage VCOM VA VB VA,B 1.4 V 1.0 V 400 mV 1.0 V 1.4 V -400 mV 1.2 V 0.8 V 400 mV 0.8 V 1.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com IOUTFS = (coarse_dac + 1)/16 x IBIAS x 64 = (coarse_dac + 1)/16 x (VEXTIO / RBIAS) / 2 x 64 where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of 1.2V. This reference is active when extref_ena = ‘0’ in config27. An external decoupling capacitor CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation.
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DAC3484 www.ti.com SLAS749C – MARCH 2011 – REVISED AUGUST 2012 ANALOG CURRENT OUTPUTS The DAC3484 can be easily configured to drive a doubly terminated 50 Ω cable using a properly selected RF transformer. Figure 88 and Figure 89 show the 50 Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable a DC current flow. Applying a 20 mA full-scale output current would lead to a 0.
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DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY Changes from Original (March 2011) to Revision A • Page Changed from PRODUCT PREVIEW to PRODUCTION DATA ........................................................................................... 1 Changes from Revision A (July 2011) to Revision B Page • Changed the revision from A, July 2011 to B, June 2012 ....................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC3484IRKDR WQFN RKD 88 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 DAC3484IRKDT WQFN RKD 88 250 330.0 16.4 9.3 9.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC3484IRKDR WQFN RKD 88 2000 336.6 336.6 28.6 DAC3484IRKDT WQFN RKD 88 250 336.6 336.6 28.
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