Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOT 23 6

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FEATURES DESCRIPTION

APPLICATIONS

SCLA0

GND

Output

Buffer

Power-Down

Control Logic

Resistor

Network

Ref (+) Ref(−)

8-Bit

DAC

Control

Logic

DAC

Power-On

Reset

OUT

SDA

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

+2.7 V to +5.5 V, I

C INTERFACE, VOLTAGE OUTPUT,

8-BIT DIGITAL-TO-ANALOG CONVERTER

• Micropower Operation: 125 µA @ 3 V

The DAC5571 is a low-power, single-channel, 8-bit

• Fast Update Rate: 188 KSPS

buffered voltage output DAC. Its on-chip precision

output amplifier allows rail-to-rail output swing to be

• Power-On Reset to Zero

achieved. The DAC5571 utilizes an I

C-compatible,

• +2.7-V to +5.5-V Power Supply

two-wire serial interface that operates at clock rates

• Specified Monotonic by Design

up to 3.4 Mbps with address support of up to two

• I

C™ Interface up to 3.4 Mbps

DAC5571s on the same data bus.

• On-Chip Output Buffer Amplifier, Rail-to-Rail

The output voltage range of the DAC is 0 V to V

Operation

The DAC5571 incorporates a power-on-reset circuit

• Double-Buffered Input Register

that ensures that the DAC output powers up at zero

• Address Support for up to Two DAC5571s

volts and remains there until a valid write to the

device takes place. The DAC5571 contains a

• Small 6 Lead SOT 23 Package

power-down feature, accessed via the internal control

• Operation From –40 °C to 105 °C

device to 50 nA at 5 V.

The low-power consumption of this part in normal

• Process Control

operation makes it ideally suited for portable battery

• Data Acquistion Systems

operated equipment. The power consumption is less

• Closed-Loop Servo Control

than 0.7 mW at V

= 5 V reducing to 1 µW in

• PC Peripherals power-down mode.

• Portable Instrumentation

DAC7571/6571/5571 are 12/10/8-bit, single-channel

C DACs from the same family. DAC7574/6574/5574

and DAC7573/6573/5573 are 12/10/8-bit

quad-channel I

C DACs. Also see DAC8571/8574 for

single/quad-channel, 16-bit I

C DACs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 +2.7 V to +5.5 V, I2C INTERFACE, VOLTAGE OUTPUT, 8-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • • • • • • • The DAC5571 is a low-power, single-channel, 8-bit buffered voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC5571 utilizes an I2C-compatible, two-wire serial interface that operates at clock rates up to 3.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted. PARAMETER CONDITIONS DAC5571 MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 8 Bits Relative accuracy Differential nonlinearity Assured monotonic by design Zero code error Full-scale error All ones loaded to DAC register ±0.5 LSB ±0.25 LSB 5 20 mV -0.15 -1.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TIMING CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS fSCL SCL Clock Frequency MIN MAX UNITS Standard mode 100 kHz Fast mode 400 kHz High-speed mode, CB - 100 pF max 3.4 MHz 1.7 MHz High-Speed mode, CB - 400 pF max tBUF tHD; tSTA tLOW tHIGH tSU; tSTA tSU; tDAT tHD; tDAT tRCL Bus Free Time Between a STOP and START Condition Standard mode 4.7 µs Fast mode 1.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TIMING CHARACTERISTICS (continued) SYMBOL PARAMETER TEST CONDITIONS tSU; tSTO Setup Time for STOP Condition Standard mode 4.0 µs Fast mode 600 ns High-speed mode 160 ns CB Capacitive Load for SDA and SCL tSP Pulse Width of Spike Suppressed VNH Noise Margin at the HIGH Level for Each Connected Device (Including Hysteresis) MIN TYP MAX UNITS 400 pF Fast mode 50 ns High-speed mode 10 ns Standard mode 0.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. SUPPLY CURRENT vs SUPPLY VOLTAGE POWER-DOWN CURRENT vs SUPPLY VOLTAGE 300 100 90 80 200 70 150 IDD (nA) I DD − Supply Current − µ A 250 100 60 +105°C 50 –40°C 40 30 50 20 0 2.7 3.2 3.7 4.2 4.7 5.2 5.7 +25°C 10 0 VDD − Supply Voltage − V 2.7 3.2 3.7 4.2 4.7 5.2 5.7 VDD (V) Figure 11. Figure 12.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME CLK (5V/div) CLK (5V/div) VOUT (1V/div) Full−Scale Code Change FF H to 00 H Output Loaded with 2k Ω and 200pF to GND Half−Scale Code Change 40 H to C0 H Output Loaded with 2k Ω and 200 pF to GND VOUT (1V/div) Time (1µ s/div) Time (1 µs/div) Figure 15. Figure 16.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. LE − LSB 0.25 0.2 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −0.25 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 DLE − LSB LE − LSB 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 DLE − LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40°C) 0.25 0.2 0.15 0.1 0.05 0 −0.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. IDD HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY 3 2500 VDD = 2.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME CLK (2.7V/div) CLK (2.7V/div) Full−Scale Code Change FFH to 00H Output Loaded with 2k Ω and 200pF to GND VOUT (1V/div) VOUT (1V/div) Time (1µs/div) Half−Scale Code Change 40 H to C0H Output Loaded with 2 k Ω and 200 pF to GND Time (1 s/div) Figure 33. Figure 34.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 THEORY OF OPERATION D/A SECTION The architecture of the DAC5571 consists of a string DAC followed by an output buffer amplifier. Figure 39 shows a block diagram of the DAC architecture. VDD REF (+) Resistor String DAC Register VOUT Output Amplifier REF (-) GND Figure 39.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 THEORY OF OPERATION (continued) Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-mode.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 THEORY OF OPERATION (continued) SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 42. Bit Transfer on the I2C Bus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition Figure 43.
PAGE 15
DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 THEORY OF OPERATION (continued) DAC5571 I2C Update Sequence The DAC5571 requires a start condition, a valid I2C address, a control-MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC5571 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the DAC5571. The CTRL/MSB byte sets the operational mode of the DAC5571, and the four most significant bits.
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DAC5571 www.ti.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 POWER-ON RESET The DAC5571 contains a power-on reset circuit that controls the output voltage during power up. On power up, the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up.
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DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 OUTPUT VOLTAGE STABILITY The DAC5571 exhibits excellent temperature stability of 5 ppm/ °C typical output voltage drift over the specified temperature range of the device. This enables the output voltage to stay within a ±25-µV window for a ±1°C ambient temperature change. Combined with good dc noise performance and true 8-bit differential linearity, the DAC5571 becomes a perfect choice for closed-loop control applications.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DAC5571IDBVR SOT-23 DBV 6 3000 178.0 9.0 DAC5571IDBVT SOT-23 DBV 6 250 178.0 9.0 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5571IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 DAC5571IDBVT SOT-23 DBV 6 250 180.0 180.0 18.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.