Datasheet

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DAC5672

www.ti.com

SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010

DUAL, 14-BIT 275 MSPS DIGITAL-TO-ANALOG CONVERTER

Check for Samples: DAC5672

FEATURES

• Low Power: 330 mW

• 14-Bit Dual Transmit Digital-to-Analog • Power-Down Mode: 9 mW

Converter (DAC)

• Package: 48-Pin Thin-Quad Flat Pack (TQFP)

• 275 MSPS Update Rate

APPLICATIONS

• Single Supply: 3 V to 3.6 V

• Cellular Base Transceiver Station Transmit

• High Spurious-Free Dynamic Range (SFDR):

Channel

84 dBc at 5 MHz

– CDMA: W-CDMA, CDMA2000, IS-95

• High Third-Order Two-Tone Intermodulation

– TDMA: GSM, IS-136, EDGE/UWC-136

(IMD3): 79 dBc at 15.1 MHz and 16.1 MHz

• Medical/Test Instrumentation

• WCDMA Adjacent Channel Leakage Ratio

• Arbitrary Waveform Generators (ARB)

(ACLR): 78 dB at Baseband

• Direct Digital Synthesis (DDS)

• WCDMA ACLR: 73 dB at 30.72 MHz

• Cable Modem Termination System (CMTS)

• Independent or Single Resistor Gain Control

• Dual or Interleaved Data

• On-Chip 1.2-V Reference

DESCRIPTION

The DAC5672 is a monolithic, dual-channel, 14-bit, high-speed DAC with on-chip voltage reference.

Operating with update rates of up to 275 MSPS, the DAC5672 offers exceptional dynamic performance,

tight-gain, and offset matching characteristics that make it suitable in either I/Q baseband or direct IF

communication applications.

Each DAC has a high-impedance, differential-current output, suitable for single-ended or differential

analog-output configurations. External resistors allow scaling the full-scale output current for each DAC

separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is

temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may

be used.

The DAC5672 has two, 14-bit, parallel input ports with separate clocks and data latches. For flexibility, the

DAC5672 also supports multiplexed data for each DAC on one port when operating in the interleaved mode.

The DAC5672 has been specifically designed for a differential transformer-coupled output with a 50-Ω

doubly-terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output

power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm output power) are supported.

The DAC5672 is available in a 48-pin TQFP package. Pin compatibility between family members provides 12-bit

(DAC5662) and 14-bit (DAC5672) resolution. Furthermore, the DAC5672 is pin compatible to the DAC2904 and

AD9767 dual DACs. The device is characterized for operation over the industrial temperature range of -40°C to

85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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DAC5672 www.ti.com SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 DUAL, 14-BIT 275 MSPS DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC5672 FEATURES 1 • • • • • • • • • • 14-Bit Dual Transmit Digital-to-Analog Converter (DAC) 275 MSPS Update Rate Single Supply: 3 V to 3.6 V High Spurious-Free Dynamic Range (SFDR): 84 dBc at 5 MHz High Third-Order Two-Tone Intermodulation (IMD3): 79 dBc at 15.1 MHz and 16.1 MHz WCDMA Adjacent Channel Leakage Ratio (ACLR): 78 dB at Baseband WCDMA ACLR: 73 dB at 30.
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM WRTB WRTA CLKB CLKA DEMUX IOUTA1 Latch A 14−b DAC DA[13:0] IOUTA2 BIASJ_A IOUTB1 Latch B DB[13:0] 14−b DAC MODE IOUTB2 BIASJ_B GSET 1.
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DAC5672 www.ti.
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over TA (unless otherwise noted) (1) UNIT AVDD (2) Supply voltage range -0.5 V to 4 V DVDD (3) -0.5 V to 4 V Voltage between AGND and DGND -0.5 V to 0.5 V Voltage between AVDD and DVDD -0.5 V to 0.5 V Supply voltage range DA[13:0] and DB[13:0] (3) -0.5 V to DVDD + 0.5 V MODE, SLEEP, CLKA, CLKB, WRTA, WRTB (3) -0.5 V to DVDD + 0.5 V IOUTA1, IOUTA2, IOUTB1, IOUTB2 (2) -1 V to AVDD + 0.
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DAC5672 www.ti.com SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) over TA, AVDD = DVDD = 3.
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS AC specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode, differential 1:1 impedance ratio transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Output fclk Maximum output update rate (1) ts Output settling time to 0.1% (DAC) tr tf 275 20 ns Output rise time 10% to 90% (OUT) 1.
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DAC5672 www.ti.com SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) AC specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode, differential 1:1 impedance ratio transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted) PARAMETER IMD Four-tone intermodulation Channel isolation TEST CONDITIONS MIN TYP MAX UNIT Each tone at -12 dBFS, TA = 25°C fDATA = 100 MSPS, fOUT = 15.6, 15.8, 16.2, and 16.
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS INL − Integral Nonlinearity Error − LSB INTEGRAL NONLINEARITY vs INPUT CODE 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 0 2000 4000 6000 8000 10000 12000 14000 Input Code 16000 G001 Figure 1. DNL − Differential Nonlinearity Error − LSB DIFFERENTIAL NONLINEARITY vs INPUT CODE 1.0 0.8 0.6 0.4 0.2 0.0 −0.2 −0.4 −0.6 −0.8 −1.0 0 2000 4000 6000 8000 10000 Input Code 12000 14000 16000 G002 Figure 2.
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DAC5672 www.ti.
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) SINGLE-TONE SPECTRUM SINGLE-TONE SPECTRUM 0 0 fdata = 165 MSPS fOUT = 30.1 MHz Dual Bus Mode fdata = 78 MSPS fOUT = 15 MHz Dual Bus Mode −20 Power − dBm Power − dBm −20 −40 −60 −40 −60 −80 −80 −100 0.0 7.8 15.6 23.4 31.2 −100 0.0 39.0 16.5 33.0 49.5 66.0 82.5 f − Frequency − MHz f − Frequency − MHz G008 G007 Figure 7. Figure 8.
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DAC5672 www.ti.com SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) TWO-TONE SPECTRUM TWO-TONE SPECTRUM fdata = 165 MSPS fdata = 78 MSPS fout1 = 20.1 MHz fout2 = 21.1 MHz Dual Bus Mode −10 −10 fout1 = 30.1 MHz fout2 = 31.1 MHz Dual Bus Mode −30 Power − dBm Power − dBm −30 −50 −70 −90 −50 −70 −90 −110 19.0 19.5 20.0 20.5 21.0 21.5 −110 29.0 22.0 29.5 f − Frequency − MHz 30.0 30.5 31.0 31.5 32.0 f − Frequency − MHz G011 G012 Figure 11.
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) POWER vs FREQUENCY POWER vs FREQUENCY −20 −40 Power − dBm Power − dBm −40 −20 fdata = 122.88 MSPS IF = 15.36 MHz ACLR = 77.16 dB Dual Bus Mode −60 −80 −100 fdata = 122.88 MSPS IF = 30.72 MHz ACLR = 72.7 dB Dual Bus Mode −60 −80 −100 −120 7.6 10.1 12.6 15.1 17.6 20.1 −120 23.0 22.6 f − Frequency − MHz 25.5 28.0 30.5 33.0 35.5 38.0 f − Frequency − MHz G015 G016 Figure 15.
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DAC5672 www.ti.com SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 DVDD 100kW GSET MODE 400W Internal Digital In DGND Figure 18. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor Input Interfaces The DAC5672 features two operating modes selected by the MODE pin, as shown in Table 1. • For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own separate data input bus, clock input, and data write signal (data latch-in).
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 DA[13:0]/DB[13:0] www.ti.com Valid Data tsu th t1ph WRTA/WRTB CLKA/CLKB tsettle tpd tlat IOUT or IOUT Figure 19. Dual-Bus Mode Operation Single-Bus Interleaved Data Interface and Timing In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 20 shows the timing diagram. In interleaved mode, the A- and B-channels share the write input (WRTIQ) and update clock (CLKIQ and internal CLKDACIQ).
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DAC5672 www.ti.com SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 DA[13:0] Valid Data tsu th SELECTIQ WRTIQ CLKIQ RESETIQ tsettle tpd tlat IOUT or IOUT Figure 20.
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 www.ti.com APPLICATION INFORMATION Theory of Operation The architecture of the DAC5672 uses a current steering technique to enable fast switching and high update rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to deliver a full-scale output current of up to 20 mA.
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DAC5672 www.ti.com SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 The total differential output voltage is: V +V *V OUTDIFF OUT1 OUT2 (2 Code * 16383) V + I OUTDIFF OUTFS 16384 (7) R LOAD (8) Analog Outputs The DAC5672 provides two complementary current outputs, IOUT1 and IOUT2. The simplified circuit of the analog output stage representing the differential topology is shown in Figure 21.
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 www.ti.com The single-ended configuration may be considered for applications requiring a unipolar output voltage. Connecting a resistor from either one of the outputs to ground converts the output current into a ground-referenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an I-to-V or op-amp configuration may be considered.
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DAC5672 www.ti.com SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 Single-Ended Configuration Figure 24 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of 25 Ω. Node IOUT2 must be connected to AGND or terminated with a resistor of 25 Ω to AGND. The nominal resistor load of 25 Ω gives a differential output swing of 1 VPP when applying a 20-mA full-scale output current. IOUT1 RLOAD 50 Ω IOUT2 50 Ω 25 Ω AGND Figure 24.
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DAC5672 SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 www.ti.com Gain Setting Option The full-scale output current on the DAC5672 can be set two ways: either for each of the two DAC channels independently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42) must be low (that is, connected to AGND). In this mode, two external resistors are required — one RSET connected to the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41).
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DAC5672 www.ti.com SLAS440C – NOVEMBER 2004 – REVISED DECEMBER 2010 REVISION HISTORY Changes from Revision B (May 2009) to Revision C • Page Changed the non-printing µ symbols in the Digital Input section of the Electrical Characteristics table (Units column) to the correct µ symbols recognized by the PDF processor. ................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC5672IPFBR Package Package Pins Type Drawing TQFP PFB 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5672IPFBR TQFP PFB 48 1000 367.0 367.0 38.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.