Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VQFN 64

DAC5681Z

www.ti.com

SLLS865F –AUGUST 2007–REVISED AUGUST 2012

16-BIT, 1.0 GSPS 2x-4x INTERPOLATING

DIGITAL-TO-ANALOG CONVERTER (DAC)

Check for Samples: DAC5681Z

FEATURES

DESCRIPTION

The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog

• 16-Bit Digital-to-Analog Converter (DAC)

converter (DAC) with wideband LVDS data input,

• 1.0 GSPS Update Rate

integrated 2x/4x interpolation filters, on-board clock

• 16-Bit Wideband Input LVDS Data Bus

multiplier and internal voltage reference. The

DAC5681Z offers superior linearity, noise, crosstalk

– 8 Sample Input FIFO

and PLL phase noise performance.

• High Performance

The DAC5681Z integrates a wideband LVDS port

– 73 dBc ACLR WCDMA TM1 at 180 MHz

with on-chip termination. Full-rate input data can be

• 2x-32x Clock Multiplying PLL/VCO

transferred to a single DAC channel, or half-rate and

• 2x or 4x Interpolation Filters

1/4-rate input data can be interpolated by on-board

2x or 4x FIR filters. Each interpolation FIR is

– Stopband Transition 0.4–0.6 Fdata

configurable in either Low-Pass or High-Pass mode,

– Filters Configurable in Either Low-Pass or

allowing selection of a higher order output spectral

High-Pass Mode

image. An on-chip delay lock loop (DLL) simplifies

– Allows Selection of Higher Order Image

LVDS interfacing by providing skew control for the

LVDS input data clock.

• On Chip 1.2 V Reference

• Differential Scalable Output: 2 to 20 mA

The DAC5681Z is characterized for operation over

the industrial temperature range of –40°C to 85°C

• Package: 64-Pin 9 × 9 mm QFN

and is available in a 64-pin QFN package. Other

members of the family include the dual-channel,

APPLICATIONS

interpolating DAC5682Z and the single-channel, non-

• Cellular Base Stations

interpolating DAC5681.

• Broadband Wireless Access (BWA)

• WiMAX 802.16

• Fixed Wireless Backhaul

• Cable Modem Termination System (CMTS)

ORDERING INFORMATION

ORDER CODE PACKAGE DRAWING/TYPE

(1) (2) (3)

TRANSPORT MEDIA QUANTITY

DAC5681ZIRGCT Tape and Reel 250

–40°C to 85°C RGC / 64QFN Quad Flatpack No-Lead

DAC5681ZIRGCR Tape and Reel 2000

(1) Thermal Pad Size: 7,4 mm × 7,4 mm

(2) MSL Peak Temperature: Level-3-260C-168 HR

(3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (58 pages)

PAGE 1
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) Check for Samples: DAC5681Z FEATURES DESCRIPTION • • • The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x/4x interpolation filters, on-board clock multiplier and internal voltage reference. The DAC5681Z offers superior linearity, noise, crosstalk and PLL phase noise performance.
PAGE 2
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. (3.3V) AVDD (1.8V) VFUSE (1.8V) DVDD LPF (1.8V) CLKVDD FUNCTIONAL BLOCK DIAGRAM PLL Bypass CLKIN Clock Multiplying PLL 2x-32x CLKINC DCLKP DCLKN 1.
PAGE 3
DAC5681Z www.ti.
PAGE 4
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION DCLKP 25 I LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased to approximately DVDD/2 and does not have an internal termination resistor in order to optimize operation of the DLL circuit. See the “DLL Operation” section. For proper external termination, connect a 100 Ω resistor across LVDS clock source lines followed by series 0.
PAGE 5
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) DVDD Supply voltage range (1) (2) VALUE UNIT –0.5 to 2.3 V VFUSE (2) –0.5 to 2.3 V CLKVDD (2) –0.5 to 2.3 V –0.5 to 4 V (2) –0.5 to 4 V AVDD to DVDD –2 to 2.6 V –0.5 to 0.5 V AVDD (2) IOVDD CLKVDD to DVDD IOVDD to AVDD –0.5 to 0.5 V –0.5 to DVDD + 0.5 V –0.3 to 2.1 V –0.5 to CLKVDD + 0.5 V –0.5 to IOVDD + 0.5 V –0.
PAGE 6
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS — DC SPECIFICATION over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, IoutFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS RESOLUTION DC ACCURACY MIN TYP MAX 16 UNIT Bits (1) INL Integral nonlinearity DNL Differential nonlinearity 1 LSB = IOUTFS/216 ±4 LSB ±2 ANALOG OUTPUT Coarse gain linearity ±0.04 LSB 0.
PAGE 7
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS — DC SPECIFICATION (continued) over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, IoutFS = 20 mA (unless otherwise noted) PARAMETER I(AVDD) Sleep mode, AVDD supply current I(DVDD) Sleep mode, DVDD supply current I(CLKVDD) Sleep mode, CLKVDD supply current I(IOVDD) Sleep mode, IOVDD supply current AVDD + IOVDD current, 3.3V DVDD + CLKVDD current, 1.
PAGE 8
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS — AC SPECIFICATION (1) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.
PAGE 9
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V.
PAGE 10
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB VIH High-level input voltage 2 3 VIL Low-level input voltage 0 0 IIH High-level input current ±20 μA IIL Low-level input current ±20 μA CI CMOS Input capacitance VOH V 0.
PAGE 11
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V.
PAGE 12
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS Figure 1. Integral Nonlinearity Figure 2.
PAGE 13
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) 90 10 -10 Power - dBm -20 SFDR - Spurious Free Dynamic Range - dBc Fdata = 1000 MSPS, FIN = 270 MHz, FOUT = 270 MHz, x1 No Interpolation PLL Off 0 -30 -40 -50 -60 -70 -80 Fdata = 1000 MSPS, No Interpolation PLL Off 85 -6 dBFS 80 75 70 -12 dBFS 65 60 -90 0 50 0 100 150 200 250 300 350 400 450 500 5 f - Frequency - MHz Figure 5.
PAGE 14
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 0 90 Fdata = 250 MSPS, FOUT = 90 MHz ±0.5 MHz, x4 Interpolation PLL Off 85 -10 -20 -30 Power - dBm 80 IMD - dBc Fdata = 500 MSPS, FOUT = 40 MHz ±0.5 MHz, x2 Interpolation PLL Off 75 -40 -50 -60 70 -70 -80 65 -90 60 -30 -24 -18 -12 Amplitude - dBFS -6 -100 38.4 0 Figure 9. Two Tone IMD vs Amplitude 38.9 39.4 39.9 40.4 f - Frequency - MHz 85 Fdata = 491.
PAGE 15
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) -20 -30 -40 -20 Fdata = 245.76 MSPS, FIN = 61.44 MHz, IF = 61.44 MHz, x4 Interpolation PLL Off -30 -40 -50 Power - dBm Power - dBm -50 -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 48.7 53.7 63.7 68.7 58.7 f - Frequency - MHz -120 48.7 73.7 Figure 13. Single Carrier W-CDMA Test Model 1 Carrier Power: -7.8 dBm, ACLR: 79.3 dB -40 58.7 63.7 f - Frequency - MHz 68.7 73.
PAGE 16
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) -20 -30 -30 -40 -50 -50 -60 -60 Power - dBm Power - dBm -40 -20 Fdata = 245.76 MSPS, FIN = 61.44 MHz, FOUT = 184.32 MHz, x4 Interpolation PLL Off -70 -80 -70 -80 -90 -90 -100 -100 -110 -110 -120 171.5 176.5 181.5 186.5 f - Frequency - MHz 191.5 -120 171.5 196.5 Figure 17. Single Carrier W-CDMA Test Model 1 Carrier Power: -8.5 dBm, ACLR: 71.8 dB -40 -30 -40 196.
PAGE 17
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) -20 -30 -40 -20 Fdata = 491.52 MSPS, FIN = 184.32 MHz, IF = 184.32 MHz, x2 Interpolation PLL Off -30 -40 -50 Power - dBm -50 Power - dBm Fdata = 491.52 MSPS, FIN = 184.32 MHz, IF = 184.32 MHz, x2 Interpolation PLL On, M/N = 2 -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 164 169 174 179 1.84 189 194 f - Frequency - MHz 199 -120 164 204 Figure 21.
PAGE 18
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TEST METHODOLOGY Typical AC specifications were characterized with the DAC5681ZEVM using the test configuration shown in Figure 25. A sinusoidal master clock frequency is generated by an HP8665B signal generator and into a splitter. One output drives an Agilent 8133A pulse generator, and the other drives the CDCM7005 clock driver.
PAGE 19
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 DEFINITION OF SPECIFICATIONS Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a 3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio. Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.
PAGE 20
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com TYPICAL APPLICATION SCHEMATIC (1) Power supply decoupling capacitors not shown. (2) Internal Reference configuration shown. Figure 26.
PAGE 21
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 DETAILED DESCRIPTION The primary modes of operation, listed in Table 1, are selected by registers CONFIG1, CONFIG2 and CONFIG3. Table 1. DAC5681Z Modes of Operation Device Config. LVDS Input Data Mode – Single Real – LP – HP X4 LP 1 X4 1X4 HP/LP 1 1X4 HP/HP 1 No.
PAGE 22
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: STATUS0 – Address: 0x00, Default = 0x0B Bit 7 Bit 6 Bit 5 PLL_lock 0 DLL_lock 0 Unused 0 Bit 4 Bit 3 0 device_ID(2:0) 1 Bit 2 Bit 1 Bit 0 version(1:0) 0 1 1 PLL_lock: Asserted when the internal PLL is locked. (Read Only) DLL_lock: Asserted when the internal DLL is locked.
PAGE 23
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG2 – Address: 0x02, Default = 0xC0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Twos_comp 1 Reserved 1 FIR2x4x 0 Unused 0 Reserved 0 FIR1_HP 0 Reserved 0 FIR0_HP 0 Twos_comp: When set (default) the input data format is expected to be 2s complement, otherwise offset binary format is expected. Reserved (Bit 6): Set to '1' for proper operation.
PAGE 24
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: STATUS4 – Address: 0x04, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unused 0 SLFTST_err 0 FIFO_err 0 Pattern_err 0 Unused 0 Unused 0 Unused 0 Unused 0 SLFTST_err: Asserted when the Digital Self Test (SLFTST) fails. To clear the error, write a ‘0’ to this register bit. This bit is also output on the SDO pin when the Self Test is enabled via SLFTST_ena control bit in CONFIG1.
PAGE 25
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG6 – Address: 0x06, Default = 0x0C Bit 7 Reserved 0 Bit 6 Unused 0 Bit 5 Reserved 0 Bit 4 Sleep_A 0 Bit 3 Bit 2 Bit 1 Bit 0 BiasLPF_A 1 Reserved 1 PLL_sleep 0 DLL_sleep 0 Reserved (Bit 7): Reserved (Bit 7): Set to 0 for proper operation. Reserved (Bit 5): Set to '0' for proper operation. Sleep_A: When set, DACA is put into sleep mode.
PAGE 26
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: CONFIG9 – Address: 0x09, Default = 0x00 Bit 7 0 Bit 6 Bit 5 0 PLL_m(4:0) 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 Bit 0 0 PLL_n(2:0) 0 0 PLL_m: M portion of the M/N divider of the PLL thermometer encoded: PLL_m(4:0) M value 00000 1 00001 2 00011 4 00111 8 01111 16 11111 32 All other values Invalid PLL_n: N portion of the M/N divider of the PLL thermometer encoded.
PAGE 27
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG10 – Address: 0x0A, Default = 0x00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 DLL_invclk 0 DLL_delay(3:0) 0 DLL_delay(3:0): 0 0 Bit 2 Bit 1 Bit 0 0 DLL_ifixed(2:0) 0 0 The DCLKP/N LVDS input data clock has a DLL to automatically skew the clock to LVDS data timing relationship, providing proper setup and hold times.
PAGE 28
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com Register name: CONFIG11 – Address: 0x0B, Default = 0x00 Bit 7 Bit 6 PLL_LPF_ reset 0 VCO_div2 0 Bit 5 Bit 4 Bit 3 PLL_gain(1:0) 0 0 0 Bit 2 Bit 1 PLL_range(3:0) 0 0 Bit 0 0 PLL_LPF_reset: When a logic high, the PLL loop filter (LPF) is pulled down to 0V. Toggle from ‘1’ to ‘0’ to restart the PLL if an over-speed lock-up occurs. Over-speed can happen when the process is fast, the supplies are higher than nominal, etc.
PAGE 29
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 Register name: CONFIG14 – Address: 0x0E, Default = 0x00 Bit 7 Bit 6 0 SDO_func_sel(2:0) 0 SDO_func_sel(2:0): Reserved (4:0): Bit 5 Bit 4 0 0 Bit 3 Bit 2 Bit 1 Bit 0 0 Reserved 0 0 0 Selects the signal for output on the SDO pin. When using the 3 pin serial interface mode, this allows the user to multiplex several status indicators onto the SDO pin.
PAGE 30
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com SERIAL INTERFACE The serial port of the DAC5681Z is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of DAC5681Z. It is compatible with most synchronous transfer formats and can be configured as a 3 or 4 pin interface by SIF4 in register CONFIG5.
PAGE 31
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 Instruction Cycle Data Transfer Cycle (s) SDENB SCLK SDIO r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 tS (SDENB) D5 D4 D3 D2 D1 D0 tSCLK SDENB SCLK SDIO tSCLKL th (SDIO) tSCLKH tS (SDIO) Figure 27. Serial Interface Write Timing Diagram Figure 28 shows the serial interface timing diagram for a DAC5681Z read operation. SCLK is the serial interface clock input to DAC5681Z. Serial data enable SDENB is an active low input to DAC5681Z.
PAGE 32
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com FIR FILTERS Figure 29 shows the magnitude spectrum response for the identical 47-tap FIR0 and FIR1 filters. The transition band is from 0.4 to 0.6 × FIN (the input data rate for the FIR filter) with <0.002 dB of pass-band ripple and approximately 76dB of stop-band attenuation. Figure 30 shows the region from 0.35 to 0.45 × FIN – up to 0.44x FIN there is less than 0.4 dB attenuation.
PAGE 33
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 Table 5.
PAGE 34
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com CLOCK AND DATA MODES There are two modes of operation to drive the internal clocks on the DAC5681Z. Timing diagrams for both modes are shown in Figure 32. EXTERNAL CLOCK MODE accepts an external full-rate clock input on the CLKIN/CLKINC pins to drive the DACs and final logic stages while distributing an internally divided down clock for lower speed logic such as the interpolating FIRs.
PAGE 35
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 PLL CLOCK MODE In PLL Clock Mode, the user provides an external reference clock to the CLKIN/C input pins. Refer to Figure 33. An internal clock multiplying PLL uses the lower-rate reference clock to generate a high-rate clock for the DAC.
PAGE 36
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com CLOCK INPUTS Figure 34 shows an equivalent circuit for the LVDS data input clock (DCLKP/N). 27 kW DVDD DCLKP Note: Input and output common mode level self-biases to approximately DVDD/2, or 0.9 V normal. DVDD GND DCLKN GND 27 kW Figure 34. DCLKP/N Equivalent Input Circuit Figure 35 shows an equivalent circuit for the DAC input clock (CLKIN/C).
PAGE 37
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 LVDS DATA INTERFACING Interfacing very high-speed LVDS data and clocks presents a big challenge to system designers as they have unique constraints and are often implemented with specialized circuits to increase bandwidth. One such specialized LVDS circuit used in many FPGAs and ASICs is a SERializer-DESerializer (SERDES) block. For interfacing to the DAC5681Z, only the SERializer functionality of the SERDES block is required.
PAGE 38
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 4x Clock Multiplier PLL Ref CLK Gen & Sync 250MHz Clock 4b SERDES (CLKOUT) 4 4b SERDES (SYNC) LVDS 4b SERDES (bit 15) LVDS 1,0,1,0...
PAGE 39
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 Example DAC5681Z D[15:0]P, SYNCP VCOM1 = (VA +VB )/2 LVDS Receiver 100 W VA,B VA VA 1.40 V VB 1.00 V V A, B 400 mV 0V D[15:0]N, SYNCN VB -400 mV GND 1 Logical Bit Equivalent 0 Figure 40. LVDS Data (D[15:0]P/N, SYNCP/N Pairs) Input Levels Table 7. Example LVDS Data Input Levels APPLIED VOLTAGES RESULTING DEFERENTIAL VOLTAGE RESULTING COMMONMODE VOLTAGE VA VB VA,B VCOM1 1.4 V 1.0 V 400 mV 1.2 V 1.0 V 1.
PAGE 40
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com DLL OPERATION The DAC5681Z provides a digital Delay Lock Loop (DLL) to skew the LVDS data clock (DCLK) relative to the data bits, D[15:0] and SYNC, in order to maintain proper setup and hold timing. Since the DLL operates closedloop, it requires a stable DCLK to maintain delay lock. Refer to the description of DLL_ifixed(2:0) and DLL_delay(3:0) control bits in the CONFIG10 register.
PAGE 41
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 CMOS DIGITAL INPUTS Figure 42 shows a schematic of the equivalent CMOS digital inputs of the DAC5681Z. SDIO and SCLK have pull-down resistors while RESETB and SDENB have pull-up resistors internal the DAC5681Z. See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ. IOVDD IOVDD internal digital in SDIO SCLK internal digital in RESETB SDENB IOGND IOGND Figure 42.
PAGE 42
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 To 1. 2. 3. 4. 5. 6. 7. 8. www.ti.com initiate a the Digital Self Test: Provide a normal CLKIN/C input clock. (The PLL is not used in SLFTST mode) Provide a RESETB pulse to perform a hardware reset on device. Program the registers with the values shown in Table 8. These register values contain the settings to properly configure the SLFTST including SLFTST_ena and SLFTST_err_mask bits Provide a ‘1’ on the SYNCP/N input to initiate TXENABLE.
PAGE 43
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 DAC TRANSFER FUNCTION The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output current up to 20 mA. Differential current switches direct the current to either one of the complementary output nodes IOUT1 or IOUT2.
PAGE 44
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com DAC OUTPUT SINC RESPONSE Due to the sampled nature of a high-speed DAC, the well known sin(x)/x (or SINC) response can significantly attenuate higher frequency output signals. Figure 43 shows the unitized SINC attenuation roll-off with respect to the final DAC sample rate in 4 Nyquist zones. For example, if the final DAC sample rate FS = 1.0 GSPS, then a tone at 440MHz is attenuated by 3.0dB.
PAGE 45
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 ANALOG CURRENT OUTPUTS Figure 44 shows a simplified schematic of the current source array output with corresponding switches in a current sink configuration. Differential switches direct the current into either the positive output node, IOUT1, or its complement, IOUT2, then through the individual NMOS current sources.
PAGE 46
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com AVDD (3.3 V) 50 W 1:1 IOUT1 RLOAD 100 W 50 W IOUT2 50 W AVDD (3.3 V) Figure 45. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer AVDD (3.3 V) 100 W 4:1 IOUT1 RLOAD 50 W IOUT2 100 W AVDD (3.3 V) Figure 46.
PAGE 47
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 where, t1 = K dK VCO w2 d (tan Φd + sec Φd ) t2 = 1 wd (tan Φd + sec Φd ) t3 = tan Φd + sec Φd wd (2) charge pump current: iqp = 1 mA vco gain: KVCO = 2π × GVCO rad/V PFD Frequency: ωd ≤160 MHz phase detector gain: Kd = iqp ÷ (2 × π × M) A/rad An Excel spreadsheet is available from Texas Instruments for automatically calculating the values for C1, R1 and C2. DAC5681Z PLL PLL LPF R1 (Pin 64) C2 C1 External Loop Filter Figure 47.
PAGE 48
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com APPLICATIONS EXAMPLES DIGITAL INTERFACE AND CLOCKING CONSIDERATIONS FOR APPLICATION EXAMPLES The DAC5681Z’s LVDS digital input bus can be driven by an FPGA or digital ASIC. This input signal can be generated directly by the FPGA, or fed by a Texas Instruments Digital Up Converter (DUC) such as the GC5016 or GC5316.
PAGE 49
DAC5681Z www.ti.com SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 APPLICATIONS EXAMPLES (continued) CMTS/VOD TRANSMITTER The exceptional SNR of the DAC5681Z enables a cable modem termination system (CMTS) or video on demand (VOD) QAM transmitter in excess of the stringent DOCSIS specification, with >74 dBc and 75 dBc in the adjacent and alternate channels.
PAGE 50
DAC5681Z SLLS865F – AUGUST 2007 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY Changes from Revision D (September 2009) to Revision E Page • Changed defined by ..... registers CONFIG1, CONFIG5 and CONFIG6 to defined by ........registers CONFIG1 and CONFIG5. ........................................................................................................................................................................... 39 • Changed in RECOMMENDED...
PAGE 51
PACKAGE OPTION ADDENDUM www.ti.
PAGE 52
PACKAGE OPTION ADDENDUM www.ti.com 1-Dec-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 53
PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC5681ZIRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 DAC5681ZIRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.
PAGE 54
PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5681ZIRGCR VQFN RGC 64 2000 336.6 336.6 28.6 DAC5681ZIRGCT VQFN RGC 64 250 336.6 336.6 28.
PAGE 55
PAGE 56
PAGE 57
PAGE 58
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.