Datasheet

DAC
I-FIR1 I-FIR0
FIFO & Demux
100
100
100
100
CLKIN
opt.
PLL
Loop
Filter
DLL
DAC5681ZDAC
CLKINC
CDCM7005
DCLK
SYNC
D0
D15
Agilent 81205A
ParBERT
Pattern
Memory
100
Opt.
Clock
Divider
DAC5681ZEVM
Stacking Interface Connector
DAC5681ZEVMSMAAdapterBoard
100
100
3.3 V
3.3 V
3.3 V
Agilent 8133A
PulseGenerator
Optional
Divider
HP8665B
Synthesized
Signal
Generator
P
N
P
N
P
N
P
N
Rohde &
Schwartz
FSU
Spectrum
Analyzer
36 each
SMA-SMAcables
Splitter
DAC5681Z
SLLS865F –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
TEST METHODOLOGY
Typical AC specifications were characterized with the DAC5681ZEVM using the test configuration shown in
Figure 25. A sinusoidal master clock frequency is generated by an HP8665B signal generator and into a splitter.
One output drives an Agilent 8133A pulse generator, and the other drives the CDCM7005 clock driver. The
8133A converts the sinusoidal frequency into a square wave output clock and drives an Agilent ParBERT
81250A pattern-generator clock. On the EVM, the DAC5681Z CLKIN/C input clock is driven by an CDCM7005
clock distribution chip that is configured to simply buffer the external 8665B clock or divide it down for PLL test
configurations.
The DAC5681Z output is characterized with a Rohde and Schwarz FSU spectrum analyzer. For WCDMA signal
characterization, it is important to use a spectrum analyzer with high IP3 and noise subtraction capability so that
the spectrum analyzer does not limit the ACPR measurement.
Figure 25. DAC5681Z Test Configuration for Normal Clock Mode
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