Datasheet

SDENB
SCLK
SDIO
SDO
SDENB
SCLK
SDIO
SDO
InstructionCycle
DataTransferCycle(s)
r/w N1 N0 - A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0
D7 D6 D5 D4 D3 D2 D1 D0 0
3pinConfigurationOutput
4pinConfigurationOutput
Datan Datan-1
t (Data)
d
InstructionCycle DataTransferCycle(s)
SDENB
SCLK
SDIO
SDENB
SCLK
SDIO
r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
t (SDENB)
S
t
SCLK
t (SDIO)
S
t (SDIO)
h
t
SCLKH
t
SCLKL
DAC5681Z
www.ti.com SLLS865F –AUGUST 2007–REVISED AUGUST 2012
Figure 27. Serial Interface Write Timing Diagram
Figure 28 shows the serial interface timing diagram for a DAC5681Z read operation. SCLK is the serial interface
clock input to DAC5681Z. Serial data enable SDENB is an active low input to DAC5681Z. SDIO is serial data in
during the instruction cycle. In 3 pin configuration, SDIO is data out from DAC5681Z during the data transfer
cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from DAC5681Z during
the data transfer cycle(s). At the end of the data transfer, SDO will output low on the final falling edge of SCLK
until the rising edge of SDENB when it will 3-state.
Figure 28. Serial Interface Read Timing Diagram
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