Datasheet

SDIO
SCLK
internal
digital in
IOVDD
IOGND
RESETB
SDENB
internal
digitalin
IOVDD
IOGND
DAC5681Z
www.ti.com SLLS865F –AUGUST 2007–REVISED AUGUST 2012
CMOS DIGITAL INPUTS
Figure 42 shows a schematic of the equivalent CMOS digital inputs of the DAC5681Z. SDIO and SCLK have
pull-down resistors while RESETB and SDENB have pull-up resistors internal the DAC5681Z. See the
specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ.
Figure 42. CMOS/TTL Digital Equivalent Input
DIGITAL SELF TEST MODE
The DAC5681Z has a Digital Self Test (SLFTST) mode to designed to enable board level testing without
requiring specific input data test patterns. The SLFTST mode is enabled via the CONFIG1 SLFTST_ena bit and
results are only valid when CONFIG3 SLFTST_err_mask bit is cleared. An internal Linear Feedback Shift
Register (LFSR) is used to generate the input test patterns for the full test cycle while a checksum result is
computed on the digital signal chain outputs. The LVDS input data bus is ignored in SLFTST mode. After the test
cycle completes, if the checksum result does not match a hardwired comparison value, the STATUS4
SLFTST_err bit is set and will remain set until cleared by writing a ‘0’ to the SLFTST_err bit. A full self test cycle
requires no more than 400,000 CLKIN/C clock cycles to complete and will automatically repeat until the
SLFTEST_ena bit is cleared.
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