Datasheet

DAC5681Z
SLLS865F –AUGUST 2007–REVISED AUGUST 2012 www.ti.com
To initiate a the Digital Self Test:
1. Provide a normal CLKIN/C input clock. (The PLL is not used in SLFTST mode)
2. Provide a RESETB pulse to perform a hardware reset on device.
3. Program the registers with the values shown in Table 8. These register values contain the settings to
properly configure the SLFTST including SLFTST_ena and SLFTST_err_mask bits
4. Provide a ‘1’ on the SYNCP/N input to initiate TXENABLE.
5. Wait at a minimum of 400,000 CLKIN/C cycles for the SLFTST to complete. Example: If CLKIN = 1GHz, then
the wait period is 400,000 × 1 / 1GHz = 400 μSec.
6. Read STATUS4 SLFTST_err bit. If set, a self test error has occurred. The SLFTST_err status may
optionally be programmed to output on the SDO pin if using the 3-bit SIF interface. See Table 8 Note (1).
7. (Optional) The SLFTST function automatically repeats until SLFTST_ena bit is cleared. To the loop the test,
write a ‘0’ to STATUS4 SLFTST_err to clear previous errors and continue at step 5 above.
8. To continue normal operating mode, provide another RESETB pulse and reprogram registers to the desired
normal settings.
Table 8. Digital Self Test (SLFTST) Register Values
REGISTER ADDRESS (hex) VALUE (Binary) VALUE (Hex)
CONFIG1 01 00011000 18
CONFIG2 02 11101010 EA
CONFIG3 03 10110000 B0
STATUS4 04 00000000 00
CONFIG5 05 00000110 06
CONFIG6 06 00001111 0F
CONFIG12 0C 00001010 0A
CONFIG13 0D 01010101 55
CONFIG14
(1)
0E 00001010 0A
CONFIG15 0F 10101010 AA
All others – Default Default
(1) If using a 3-bit SIF interface, the SDO pin can be programmed to report SLFTST_err status via the SDO_fun_sel(2:0) bits. In this case,
set CONFIG14 = ‘10101010’ or AA hex.
REFERENCE OPERATION
The DAC5681Z uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-
scale output current is set by applying an external resistor R
BIAS
to pin BIASJ. The bias current I
BIAS
through
resistor R
BIAS
is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale
output current equals 16 times this bias current and can thus be expressed as:
IOUT
FS
= 16 × I
BIAS
= 16 × V
EXTIO
/ R
BIAS
The DAC has a 4-bit coarse gain control via DACA_gain(3:0) in the CONFIG7 register so the IOUT
FS
can
expressed as:
IOUTA
FS
= (DACA_gain + 1) × I
BIAS
= (DACA_gain + 1) × V
EXTIO
/ R
BIAS
where V
EXTIO
is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of
1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
C
EXT
of 0.1 μF should be connected externally to terminal EXTIO for compensation. The bandgap reference can
additionally be used for external reference operation. In that case, an external buffer with high impedance input
should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can
be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may
hence be omitted. Terminal EXTIO thus serves as either input or output node.
The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor R
BIAS
or changing the
externally applied reference voltage. The internal control amplifier has a wide input range, supporting the full-
scale output current range of 20 dB.
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