Datasheet

DAC5681Z
www.ti.com SLLS865F –AUGUST 2007–REVISED AUGUST 2012
DAC TRANSFER FUNCTION
The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output
current up to 20 mA. Differential current switches direct the current to either one of the complementary output
nodes IOUT1 or IOUT2. Complementary output currents enable differential operation, thus canceling out
common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion
components, and increasing signal output power by a factor of two.
The full-scale output current is set using external resistor R
BIAS
in combination with an on-chip bandgap voltage
reference source (+1.2 V) and control amplifier. Current I
BIAS
through resistor R
BIAS
is mirrored internally to
provide a maximum full-scale output current equal to 16 times I
BIAS
.
The relation between IOUT1 and IOUT2 can be expressed as:
IOUT1 = – IOUT
FS
– IOUT2
We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the
output stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. The output
current flow in each pin driving a resistive load can be expressed as:
IOUT1 = IOUT
FS
× (65535 – CODE) / 65536
IOUT2 = IOUT
FS
× CODE / 65536
where CODE is the decimal representation of the DAC data input word.
For the case where IOUT1 and IOUT2 drive resistor loads R
L
directly, this translates into single ended voltages
at IOUT1 and IOUT2:
VOUT1 = AVDD – | IOUT1 | × R
L
VOUT2 = AVDD – | IOUT2 | × R
L
Assuming that the data is full scale (65536 in offset binary notation) and the R
L
is 25 Ω, the differential voltage
between pins IOUT1 and IOUT2 can be expressed as:
VOUT1 = AVDD – | –0 mA | × 25 Ω = 3.3 V
VOUT2 = AVDD – | –20 mA | × 25 Ω = 2.8 V
VDIFF = VOUT1 – VOUT2 = 0.5 V
Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would
lead to increased signal distortion.
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