Datasheet

DAC5681Z
www.ti.com SLLS865F –AUGUST 2007–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS — DC SPECIFICATION (continued)
over operating free-air temperature range , AVDD = 3.3 V, CLKVDD = 1.8 V, IOVDD = 3.3 V, DVDD = 1.8 V, Iout
FS
= 20 mA
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
(AVDD)
Sleep mode, AVDD supply current 1 mA
I
(DVDD)
Sleep mode, DVDD supply current 4 mA
Sleep mode, CLKVDD supply
Mode 6 (below)
I
(CLKVDD)
2 mA
current
I
(IOVDD)
Sleep mode, IOVDD supply 2 mA
current
AVDD + IOVDD current, 3.3V Mode 1: 1X2, PLL = OFF, CLKIN = 983.04 MHz 71 mA
FDAC = 983.04MHz, IF = 184.32 MHz
DVDD + CLKVDD current, 1.8V 267 mA
4 carrier WCDMA
Power Dissipation 715 mW
AVDD + IOVDD current, 3.3V Mode 2: 1X2, PLL = ON (8X), CLKIN = 122.88 MHz 81 mA
FDAC = 983.04MHz, IF = 184.32 MHz
DVDD + CLKVDD current, 1.8V 292 mA
4 carrier WCDMA
Power Dissipation 790 mW
AVDD + IOVDD current, 3.3V Mode 3: 1X4, HP/HP, PLL = OFF, 71 mA
CLKIN = 983.04 MHz, FDAC = 983.04MHz,
DVDD + CLKVDD current, 1.8V 278 mA
IF = 215.04 MHz
735
Power Dissipation mW
4 carrier WCDMA
P
AVDD + IOVDD current, 3.3V Mode 4: 1X4, HP/HP, PLL = ON (8X), 81 mA
CLKIN = 122.88 MHz
DVDD + CLKVDD current, 1.8V 312 mA
FDAC = 983.04MHz, IF = 215.04 MHz
830 910
Power Dissipation mW
DACA on, 4 carrier WCDMA
AVDD + IOVDD current, 3.3V Mode 5: PLL = OFF, 3 mA
CLKIN = 983.04 MHz, FDAC = 983.04MHz,
DVDD + CLKVDD current, 1.8V 117 mA
Digital Logic Disabled, DAC on SLEEP,
220
Power Dissipation mW
Static Data Pattern
AVDD + IOVDD current, 3.3V Mode 6: PLL = OFF, CLKIN = OFF 3 mA
FDAC = OFF, Digital Logic Disabled
DVDD + CLKVDD current, 1.8V 6 mA
DAC on SLEEP, Static Data Pattern
Power Dissipation 20 30 mW
PSRR Power supply rejection ratio DC tested –0.2 0.2 %FSR/V
T Operating range –40 85 °C
ANALOG OUTPUT
f
CLK
Maximum output update rate 1000 MSPS
t
s(DAC)
Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10.4 ns
DAC output is updated on falling edge of DAC clock.
t
pd
Output propagation delay 2.5 ns
Does not include Digital Latency (see below).
t
r(IOUT)
Output rise time 10% to 90% 220 ps
t
f(IOUT)
Output fall time 90% to 10% 220 ps
No interpolation, PLL Off 76
DAC
Digital Latency x2 interpolation, PLL Off 158 clock
cycles
x4 interpolation, PLL Off 289
IOUT current settling to 1% of IOUT
FS
. Measured
DAC Wake-up Time 80 μs
from SDENB; Register 0x06, toggle Bit 4 from 1 to 0.
Power-up
IOUT current settling to less than 1% of IOUT
FS
.
Time
DAC Sleep Time Measured from SDENB; Register 0x06, toggle Bit 4 80 μs
from 0 to 1.
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