Datasheet

DAC5681Z
www.ti.com SLLS865F –AUGUST 2007–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)
over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS INTERFACE: D[15:0]P/N, SYNCP/N, DCLKP/N
(1)
Logic high differential
V
A,B+
175 mV
input voltage threshold
Logic low differential
V
A,B–
–175 mV
input voltage threshold
V
COM1
Input Common Mode SYNCP/N, D[15:0]P/N only 1.0 V
DCLKP/N only DVDD
V
COM2
Input Common Mode V
÷2
Z
T
Internal termination SYNCP/N, D[15:0]P/N only 85 110 135 Ω
LVDS Input
C
L
2 pF
capacitance
DCLKP/N: 0 to 125MHz (see Figure 32) DLL Disabled, Setup_min 1100
t
S
, t
H
DCLK to Data ps
CONFIG5 DLL_bypass = 1, CONFIG10 = '00000000'
Hold_min –600
Positive 1000
DCLKP/N = 150 MHz
Negative –1800
Positive 800
DCLKP/N = 200 MHz
Negative –1300
Positive 600
DCLKP/N = 250 MHz
Negative –1000
Positive 450
DCLKP/N = 300 MHz
DLL Enabled,
Negative –800
t
SKEW(A),
DCLK to Data Skew
(2)
CONFIG5 DLL_bypass = 0, ps
t
SKEW(B)
Positive 400
DDR format
DCLKP/N = 350 MHz
Negative –700
Positive 300
DCLKP/N = 400 MHz
Negative –600
Positive 300
DCLKP/N = 450 MHz
Negative –500
Positive 350
DCLKP/N = 500 MHz
Negative –300
DLL Disabled, CONFIG5 DLL_bypass = 1, DDR format,
250
DCLKP frequency: <125 MHz
Input data rate
f
DATA
MSPS
supported
DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format,
250 1000
DCLKP frequency: 125 to 500 MHz
CONFIG10 = '11001101' = 0xCD 125-150
CONFIG10 = '11001110' = 0xCE 150-175
DLL Operating
DLL Enabled, CONFIG5
Frequency (DCLKP/N CONFIG10 = '11001111' = 0xCF 175-200 MHz
DLL_bypass = 0, DDR format
Frequency)
CONFIG10 = '11001000' = 0xC8 200-325
CONFIG10 = '11000000' = 0xC0 325-500
(1) See LVDS INPUTS section for terminology.
(2) Positive skew: Clock ahead of data.
Negative skew: Data ahead of clock.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DAC5681Z