Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) HTQFP 100

FEATURES

APPLICATIONS

DESCRIPTION

DAC5686

www.ti.com

............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009

16-BIT, 500-MSPS, 2 × – 16 × INTERPOLATING DUAL-CHANNEL

DIGITAL-TO-ANALOG CONVERTER

• 1.8-V Digital and 3.3-V Analog Supplies

234

• 500-MSPS Maximum-Update-Rate DAC • 1.8-V/3.3-V CMOS-Compatible Interface

• WCDMA ACPR • Power Dissipation: 950 mW at Full Maximum

Operating Conditions

– 1 Carrier: 76 dB Centered at 30.72-MHz IF,

245.76 MSPS • Package: 100-Pin HTQFP

– 1 Carrier: 73 dB Centered at 61.44-MHz IF,

245.76 MSPS

• Cellular Base Transceiver Station Transmit

– 2 Carrier: 72 dB Centered at 30.72-MHz IF,

Channel

245.76 MSPS

– CDMA: W-CDMA, CDMA2000, IS-95

– 4 Carrier: 64 dB Centered at 92.16-MHz IF,

– TDMA: GSM, IS-136, EDGE/UWC-136

491.52 MSPS

• Baseband I and Q Transmit

• Selectable 2 × , 4 × , 8 × , and 16 × Interpolation

• Input Interface: Quadrature Modulation for

– Linear Phase

Interfacing With Baseband Complex Mixing

– 0.05-dB Pass-Band Ripple

ASICs

– 80-dB Stop-Band Attenuation

• Single-Sideband Up-Conversion

• Diversity Transmit

– Stop-Band Transition 0.4 – 0.6 f

DATA

• Cable Modem Termination System

• 32-Bit Programmable NCO

• On-Chip 2 × – 16 × PLL Clock Multiplier With

Bypass Mode

• Differential Scalable Current Outputs: 2 mA to

20 mA

• On-Chip 1.2-V Reference

The DAC5686 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2 × , 4 × , 8 × ,

and 16 × interpolation filters, a numerically controlled oscillator (NCO), onboard clock multiplier, and on-chip

voltage reference. The DAC5686 has been specifically designed to allow for low input data rates between the

DAC and ASIC, or FPGA, and high output transmit intermediate frequencies (IF). Target applications include

high-speed digital data transmission in wired and wireless communication systems and high-frequency

direct-digital synthesis DDS.

The DAC5686 provides three modes of operation: dual-channel, single-sideband, and quadrature modulation. In

dual-channel mode, interpolation filtering increases the DAC update rate, which reduces sinx/x rolloff and

enables the use of relaxed analog post-filtering.

Single-sideband mode provides an alternative interface to the analog quadrature modulators. Channel carrier

selection is performed at baseband by mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are

input to the DAC5686, which in turn performs a complex mix resulting in Hilbert transform pairs at the outputs of

the DAC5686 ' s two DACs. An external RF quadrature modulator then performs the final single-sideband

up-conversion. The DAC5686 ' s complex mixing frequencies are flexibly chosen with the 32-bit programmable

NCO.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD is a trademark of Texas Instruments.

3 Excel is a trademark of Microsoft Corporation.

4 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (53 pages)

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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 16-BIT, 500-MSPS, 2×–16× INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER FEATURES 1 • 500-MSPS Maximum-Update-Rate DAC • WCDMA ACPR – 1 Carrier: 76 dB Centered at 30.72-MHz IF, 245.76 MSPS – 1 Carrier: 73 dB Centered at 61.44-MHz IF, 245.76 MSPS – 2 Carrier: 72 dB Centered at 30.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local oscillator feedthrough.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 FUNCTIONAL BLOCK DIAGRAM Block Diagram of the DAC5686 CLKVDD CLKGND PLLLOCK PLLGND LPF PLLVDD PHSTR SLEEP DVDD CLK1 1.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 DEVICE INFORMATION Terminal Functions TERMINAL NAME NO.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION SDIO 30 I/O Bidirectional serial-port data in the three-pin serial interface mode. Input-only serial data in the four-pin serial interface mode.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (1) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (continued) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (1) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (continued) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) DNL – Differential Nonlinearity Error – LSB DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE 15 13 11 9 7 5 3 1 –1 0 10000 20000 30000 40000 50000 60000 70000 Input Code G002 Figure 2.
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DAC5686 www.ti.com ............................................................................................................................................................
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) TWO-TONE IMD3 vs OUTPUT FREQUENCY TWO-TONE IMD PERFORMANCE 0 90 fDATA = 80 MSPS NCO On Quad Mode 4y Interpolation PLLVDD = 0 V 80 −20 −30 Power – dBm Two-Tone IMD3 – dBc 85 fDATA = 80 MSPS fIN1 = –0.5 MHz fIN2 = 0.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS (continued) WCDMA TEST MODEL 1: DUAL CARRIER WCDMA TEST MODEL 1: DUAL CARRIER −20 −30 −40 fDATA = 122.88 MSPS fIN = 30.72 MHz ACLR = 71.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) VCO GAIN vs VCO FREQUENCY 600 Boost for 0% GVCO – VCO Gain – MHz/V 500 400 300 Boost for 45% 200 100 Boost for 30% Boost for 15% 0 0 100 200 300 400 500 fVCO – VCO Frequency – MHz 600 700 G017 Figure 17.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 DETAILED DESCRIPTION Dual-Channel Mode In dual-channel mode, interpolation filtering increases the DAC update rate, thereby reducing sinx/x rolloff and enabling relaxed analog post-filtering, and is useful for baseband I and Q modulation or two-channel low-IF signals.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com fDATA cos DEMUX A Offset + DA[15:0] 2y–16y fDATA FIR5 y2–y16 A sin DB[15:0] x sin(x) +/− A Gain + B Gain 16-Bit DAC IOUTA1 16-Bit DAC IOUTB1 IOUTA2 y2–y16 sin B cos x sin(x) IOUTB2 + B Offset B0021-01 Figure 19.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 DAC5686 cos(wct) I A(t) = I(t)cos(wct) – Q(t)sin(wct) + A sin(wct) – DAC Q cos(wLOt) IF(t) = I(t)cos(wc + wLO)t – Q(t)sin(wc + wLO)t sin(wct) DAC + cos(wct) B sin(wLOt) 0° 90° Quadrature Modulator + LO B(t) = I(t)sin(wct) + Q(t)cos(wct) B0022–01 Figure 20.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Complex Input Spectrum to DAC5686 0 –ωc Complex Input Spectra to Quadrature Modulator –ωc –ωc –ωc 0 0 0 0 ω ωc ωc ωc ωc ω ω ω ω rspect = 0 ssb = 0 rspect = 0 ssb = 1 rspect = 1 ssb = 1 rspect = 1 ssb = 0 M0017-01 Figure 22.
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DAC5686 www.ti.com ............................................................................................................................................................
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com cos sin fDATA FIR1 DEMUX FIR2 FIR3 FIR4 2y–16y fDATA y2 DA[15:0] y2 y2 y2 + FIR5 x sin(x) FIR1 FIR2 FIR3 FIR4 16-Bit DAC B Offset y2 y2 IOUTB2 +/− DB[15:0] y2 IOUTB1 B Gain y2 sin cos B0023-01 Figure 23.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 Table 1. Instruction Byte of the Serial Interface (continued) MSB Description R/W LSB N1 N0 – A3 A2 A1 A0 R/W: Identifies the following data transfer cycle as a read or write operation.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial data-in during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the DAC5686 during the data transfer cycle(s), while SDO is in a high-impedance state.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 In PLL CLOCK MODE, the DAC is driven at the input sample rate (unless the data is multiplexed) through CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC generates the higher-speed DAC sample-rate clock using an internal PLL/VCO.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com LPF DIV[1:0] PLLVDD CLK1 CLK1C Clk Buffer Charge Pump PFD /1 /2 /4 /8 VCO CLK2 CLK2C clk_16y DAC Sample Clock Clk Buffer /2 clk_8y /2 clk_4y /2 clk_2y /2 clk_1y PLLVDD PLLGND 0 CLKVDD CLKGND 1 s PLLLOCK PLLVDD Data D[15:0] SEL[1:0] B0024-01 Figure 27.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 Table 3. Clock-Mode Configuration (continued) CLOCK MODE PLLVDD DIV[1:0] SEL[1:0] DATA RATE (MSPS) PLLLOCK PIN FUNCTION Non-interleaved input data; internal PLL on; DA[15:0] data rate matches DB[15:0] data rate. Internal 2× 3.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Figure 28(b) shows the location of the largest spurious signals for fDAC = 500 MSPS and 4× interpolation for a real output signal.
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DAC5686 www.ti.com ............................................................................................................................................................
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Figure 30 shows the DAC5686 output spectrum for the preceding example. The amplitudes of the clock-related spurs agree quite well with the predicted amplitudes in Table 4.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 CLK1 ts(DATA) th(DATA) DA[15:0] A0 A1 A2 A3 AN AN+1 DB[15:0] B0 B1 B2 B3 BN BN+1 T0039-01 Figure 32. Dual-Bus Mode Timing Diagram (PLL Mode) PLLLOCK td(PLLLOCK) CLK2 ts(DATA) th(DATA) DA[15:0] A0 A1 A2 A3 AN AN+1 DB[15:0] B0 B1 B2 B3 BN BN+1 T0040-01 Figure 33.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com TXENABLE ts(TXENABLE) CLK1 or PLLLOCK ts(DATA) th(DATA) DA[15:0] A0 B0 A1 B1 AN BN T0041-01 Figure 35. Interleave Bus Mode Timing Diagram Using TxENABLE Interleaved user data on data bus DA is alternately multiplexed to internal data channels A and B.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 CLK2 CLK2C PLLLOCK T0003-01 Figure 37. Four Possible PLLLOCK Phases for N = 4 in External Clock Mode To synchronize PLLLOCK input clocks across multiple DAC5686 chips, a synchronization signal on the PHSTR pin is used.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com The PHSTR transition has a setup and hold time relative to the DAC output sample clock (ts_PHSTR and th_PHSTR) equal to 50% of the DAC output sample clock period up to a maximum of 1 ns. At 500 MHz, the setup and hold times are therefore 0.5 ns.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 MAGNITUDE vs FREQUENCY 20 20 0 0 −20 −20 −40 −40 Magnitude – dB Magnitude – dB MAGNITUDE vs FREQUENCY −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 0.0 −160 0.5 1.0 1.5 2.0 2.5 3.0 3.5 f/fDATA 0 4.0 1 2 3 4 5 6 7 f/fDATA G025 Figure 41.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com The filter taps for interpolation filters FIR1–FIR4 and inverse sinc filter FIR5 are listed in Table 5. Table 5.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 Table 5. Filter Taps for FIR1–FIR5 (continued) FIR1 FIR2 FIR3 FIR4 FIR5 (INVSINC) 0 58 0 –24 0 8 NCO The DAC5686 uses a numerically controlled oscillator (NCO) with a 32-bit frequency register and a 16-bit phase register.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.
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DAC5686 www.ti.com ............................................................................................................................................................
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com sel[1:0]: Controls the selection of interpolating filters used; summarized in Table 8. Table 8. DAC5686 Filter Configuration sel[1:0] INTERP.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 ensure that max(abs(cos(ωt) + sin(ωt))) < 1. At different frequencies, the summation produces different maximum outputs and must be reduced. The simplest is fDAC/4 mode where the maximum is 1 and the gain multiply should be 1 to maintain unity.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com sleepa: When asserted, DACA is put into the sleep mode.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 IOVDD DA[15:0] DB[15:0] SLEEP PHSTR TXENABLE QFLAG SDIO SCLK SDENB IOVDD 100 kW 400 W 400 W Internal Digital In Internal Digital In RESETB 100 kW IOGND IOGND S0027–02 Figure 45.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Optional, May Be Bypassed for Sine Wave Input Swing Limitation CAC 0.1 µF 1:4 CLK RT 200 Ω CLKC Termination Resistor S0029-01 Figure 47. Preferred Clock Input Configuration Ropt 22 Ω CAC 0.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 DAC Transfer Function The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output current up to 20 mA. Differential current switches direct the current of each current source through either one of the complementary output nodes IOUT1 or IOUT2.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Analog Current Outputs Figure 50 shows a simplified schematic of the current source array with corresponding switches. Differential switches direct the current of each individual NMOS current source to either the positive output node IOUT1 or its complementary negative output node IOUT2.
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DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 AVDD (3.3 V) 50 Ω 1:1 IOUT1 RLOAD 50 Ω 100 Ω IOUT2 50 Ω AVDD (3.3 V) S0033-01 Figure 51. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance-Ratio Transformer AVDD (3.3 V) 100 Ω 4:1 IOUT1 RLOAD 50 Ω IOUT2 100 Ω AVDD (3.3 V) S0033-02 Figure 52.
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com DAC5686 EVALUATION BOARD There is a combination EVM board for the DAC5686 digital-to-analog converter for evaluation. This board allows the user the flexibility to operate the DAC5686 in various configurations.
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DAC5686 www.ti.com ............................................................................................................................................................
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DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Revision History Changes from Revision E (June 2006) to Revision F ..................................................................................................... Page • • • • • • • • • • • • • • Changed DA[15:0] pin description .........................................................
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PACKAGE OPTION ADDENDUM www.ti.com 6-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC5686IPZP ACTIVE HTQFP PZP 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC5686IPZPG4 ACTIVE HTQFP PZP 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.