Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) HTQFP 100

FEATURES DESCRIPTION

APPLICATIONS

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

www.ti.com

16-BIT, 500 MSPS 2 × – 8 × INTERPOLATING DUAL-CHANNEL

DIGITAL-TO-ANALOG CONVERTER (DAC)

2345

• 500 MSPS

The DAC5687 is a dual-channel 16-bit high-speed

digital-to-analog converter (DAC) with integrated 2 × ,

• Selectable 2 × – 8 × Interpolation

4 × , and 8 × interpolation filters, a complex numerically

• On-Chip PLL/VCO Clock Multiplier

controlled oscillator (NCO), onboard clock multiplier,

• Full IQ Compensation Including Offset, Gain,

IQ compensation, and on-chip voltage reference. The

and Phase

DAC5687 is pin-compatible to the DAC5686,

• Flexible Input Options:

requiring only changes in register settings for most

– FIFO With Latch on External or Internal

applications, and offers additional features and

Clock

superior linearity, noise, crosstalk, and PLL phase

noise performance.

– Even/Odd Multiplexed Input

The DAC5687 has six signal processing blocks: two

– Single Port Demultiplexed Input

interpolate-by-two digital filters, a fine frequency

• Complex Mixer With 32-Bit NCO

mixer with 32-bit NCO, a quadrature modulation

• Fixed Frequency Mixer With f

/4 and f

compensation block, another interpolate-by-two digital

• 1.8-V or 3.3-V I/O Voltage

filter, and a coarse frequency mixer with f

/2 or f

/4.

The different modes of operation enable or bypass

• On-Chip 1.2-V Reference

the signal processing blocks.

• Differential Scalable Output: 2 mA to 20 mA

The coarse and fine mixers can be combined to span

• Pin Compatible to DAC5686

a wider range of frequencies with fine resolution. The

• High Performance

DAC5687 allows both complex or real output.

– 81-dBc ACLR WCDMA TM1 at 30.72 MHz

Combining the frequency upconversion and complex

output produces a Hilbert transform pair that is output

– 72-dBc ACLR WCDMA TM1 at 153.6 MHz

from the two DACs. An external RF quadrature

• Package: 100-Pin HTQFP

modulator then performs the final single-sideband

upconversion.

The IQ compensation feature allows optimization of

• Cellular Base Transceiver Station Transmit

phase, gain, and offset to maximize sideband

Channel

rejection and minimize LO feedthrough for an analog

– CDMA: W-CDMA, CDMA2000, TD-SCDMA

quadrature modulator.

– TDMA: GSM, IS-136, EDGE/UWC-136

The DAC5687 includes several input options:

– OFDM: 802.16

single-port interleaved data, even and odd

• Cable Modem Termination System

multiplexing at half-rate, and an input FIFO with either

external or internal clock to ease the input timing

ambiguity when the DAC5687 is clocked at the DAC

output sample rate.

ORDERING INFORMATION

Package Device

100 HTQFP

(1)

(PZP) PowerPAD™

package, plastic quad flatpack

– 40 ° C to 85 ° C

DAC5687IPZP

(1) Thermal pad size: 6 mm × 6 mm.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD is a trademark of Texas Instruments.

3 Excel is a trademark of Microsoft Corporation.

4 Matlab is a trademark of The MathWorks, Inc.

5 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (79 pages)

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DAC5687 www.ti.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM CLKVDD CLKGND PLLGND LPF PLLVDD PHSTR SLEEP DVDD CLK1 CLK1C 1.
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DAC5687 www.ti.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AGND 1, 4, 7, 9, 12, 17, 19, 22, 25 I Analog ground return AVDD 2, 3, 8, 10, 14, 16, 18, 23, 24 I Analog supply voltage BIASJ 13 O Full-scale output current bias CLK1 59 I In PLL clock mode and dual clock modes, provides data input rate clock. In external clock mode, provides optional input data rate clock to FIFO latch.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. SLEEP 96 I/O DESCRIPTION I Asynchronous hardware power-down input. Active-High. Internal pulldown. TXENABLE 33 I TXENABLE has two purposes. In all modes, TXENABLE must be high for the DATA to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data presented to DA[15:0] and DB[15:0] is ignored.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 THERMAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) Thermal Conductivity θJC Theta junction-to-case 100 HTQFP UNIT 0.12 °C/W ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 19.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 19.2 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD Analog supply voltage 3 3.3 3.6 V DVDD Digital supply voltage 1.71 1.8 2.15 V CLKVDD Clock supply voltage 3 3.3 3.6 V 3.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (1) over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V (= 3.3 V for PLL clock mode), IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 19.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V (= 3.3 V for PLL clock mode), IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 19.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 19.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Typical Characteristics 8 6 6 4 2 2 Error − LSB Error − LSB 4 0 −2 0 −2 −4 −4 −6 −8 −6 0 10000 20000 30000 40000 50000 60000 70000 0 10000 20000 30000 40000 50000 60000 70000 Code Code G001 G002 Figure 1. Integral Nonlinearity Figure 2.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Typical Characteristics (continued) 100 10 0 −10 P − Power − dBm −20 SFDR − Spurious-Free Dynamic Range − dBc fdata = 125 MSPS fin = 30 MHz Real IF = 155 MHz y4L Interpolation HP/HP PLL Off −30 −40 −50 −60 −70 −80 −90 fdata = 125 MSPS y4 Interpolation PLL Off 95 90 −6 dBFS 85 80 75 0 dBFS −12 dBFS 70 65 60 0 50 100 150 200 5 250 f − Frequency − MHz 10 15 20 25 30 G005 G006 Figure 5.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Typical Characteristics (continued) 90 80 IMD3 − dBC 75 −20 −30 70 65 60 −40 −50 −60 55 −70 50 −80 45 −90 40 −35 −30 −25 −20 −15 fdata = 125 MSPS fin = 20 MHz +0.5 MHz Real IF = 20 MHz y4 Interpolation PLL Off −10 P − Power − dBm 85 0 fdata = 125 MSPS fin = −30 MHz +0.5 MHz Complex IF = 95 MHz y4L Interpolation CMIX PLL Off −10 −5 −100 10 0 15 Amplitude − dBFS 20 25 G009 G010 Figure 9.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Typical Characteristics (continued) −10 −20 −30 −20 −30 −40 −50 P − Power − dBm P − Power − dBm −40 −10 Carrier Power: −7.99 dBm ACLR (5 MHz): 81.24 dB ACLR (10 MHz): 83.79 dB fdata = 122.88 MSPS IF = 30.72 MHz y4 Interpolation −60 −70 −80 −90 −50 −60 −70 −80 −90 −100 −100 −110 −110 −120 −120 −130 18 23 28 33 38 Carrier Power: −7.99 dBm ACLR (5 MHz): 75.8 dB ACLR (10 MHz): 80.18 dB fdata = 122.88 MSPS IF = 30.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Typical Characteristics (continued) −20 −30 P − Power − dBm −40 −50 −10 Carrier Power: −10.35 dBm ACLR (5 MHz): 72.06 dB ACLR (10 MHz): 73.21 dB fdata = 122.88 MSPS IF = 153.6 MHz y4 Interpolation CMIX −20 −30 −40 P − Power − dBm −10 −60 −70 −80 −90 −50 −60 −70 −80 −90 −100 −100 −110 −110 −120 −120 −130 141 146 151 156 161 Carrier Power: −10.35 dBm ACLR (5 MHz): 63.12 dB ACLR (10 MHz): 69.17 dB fdata = 122.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Typical Characteristics (continued) −20 −30 −40 −40 −50 −50 P − Power − dBm P − Power − dBm −30 −20 Carrier Power 1 (Ref): −17.41 dBm ACLR (5 MHz): 69.09 dB ACLR (10 MHz): 69.34 dB −60 −70 −80 −90 −100 Carrier Power 1 (Ref): −17.42 dBm ACLR (5 MHz): 64 dB ACLR (10 MHz): 65.79 dB −60 −70 −80 −90 −100 −110 −110 fdata = 122.88 MSPS IF = 92.16 MHz y4 Interpolation CMIX −120 −130 72 77 82 87 92 97 fdata = 122.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Typical Characteristics (continued) −20 −30 Carrier Power 1 (Ref): −19.88 dBm ACLR (5 MHz): 66.6 dB ACLR (10 MHz): 65.73 dB −40 P − Power − dBm −50 −60 −70 −80 −90 −100 −110 fdata = 122.88 MSPS IF = 153.6 MHz y4 Interpolation CMIX −120 −130 133 138 143 148 153 158 163 168 173 f − Frequency − MHz G025 Figure 25. WCDMA TM1: Four Carriers, PLL Off, DVDD = 2.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 1.8 V/2.1 V 200 Ω Mini Circuits TCM4−1W CLK2C CLK1 CLK1C PULSE FREQ. = fdata 10 pF DVDD (Pin 56) SLEEP CLK2 DVDD (Not Including Pin 56) PULSE FREQ. = fDAC Ampl. = 1 VPP 1:4 PHSTR 0.01 µF Agilent 8133A Pulse Generator PLLGND Sinusoid FREQ. = fDAC PLLVDD 10 Ω DGND HP8665B Synthesized Signal Generator EXTLO BIASJ 3.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 1.8 V/2.1 V 3.3 V 200 Ω Mini Circuits TCM4−1W CLK1C CLK2 CLK2C PULSE FREQ. = fdata 10 pF DVDD (Pin 56) SLEEP CLK1 DVDD (Not Including Pin 56) PULSE FREQ. = fdata Ampl. = 1 VPP 1:4 PHSTR 0.01 µF Agilent 8133A Pulse Generator PLLGND Sinusoid FREQ. = fdata PLLVDD 10 Ω DGND HP8665B Synthesized Signal Generator EXTLO BIASJ 3.
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DAC5687 www.ti.com Cummulative Complementary Distribution Function SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 100 10−2 2 Carriers 4 Carriers 1 Carrier 10−4 10−6 3 5 7 9 11 13 15 Peak-to-Average Ratio − dB G041 Figure 28.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Table 1.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 A Offset FIR1 FIR4 FIR2 Quadrature Mod Correction (QMC) Fine Mixer Input Formatter FIR1 y2 FIR2 DB[15:0] y2 x sin(x) 16-Bit DAC x sin(x) 16-Bit DAC IOUTA1 IOUTA2 Course Mixer: fs/2 or fs/4 DA[15:0] y2 A Gain y2 IOUTB1 IOUTB2 sin cos B Offset NCO B Gain B0161-01 A. FMIX or QMC block cannot be enabled with CMIX block. Figure 30.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 A Offset FIR1 FIR2 FIR4 FIR3 y2 Fine Mixer y2 x sin(x) 16-Bit DAC x sin(x) 16-Bit DAC IOUTA1 IOUTA2 Course Mixer: fs/2 or fs/4 y2 Input Formatter y2 Quadrature Mod Correction (QMC) DA[15:0] y2 A Gain DB[15:0] y2 IOUTB1 IOUTB2 sin cos NCO B Offset B Gain B0163-01 Figure 32.
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DAC5687 www.ti.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Register Name: CONFIG0—Address: 0x01, Default = 0x00 BIT 7 BIT 0 pll_div(1:0) 0 0 pll_freq pll_kv 0 0 interp(1:0) 0 0 inv_plllock fifo_bypass 0 0 pll_div(1:0): PLL VCO divider; {00 = 1, 01 = 2, 10 = 4, 11 = 8}. pll_freq: PLL VCO center frequency; {0 = low center frequency, 1 = high center frequency}. pll_kv: PLL VCO gain; {0 = high gain, 1 = low gain}. interp(1:0): FIR interpolation; {00 = X2, 01 = X4, 10 = X4L, 11 = X8}.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 input data MSB to LSB order is reversed, DA[15] = LSB and DA[0] = MSB. rev_bbus: When cleared, DB input data MSB to LSB order is DB[15] = MSB and DB[0] = LSB. When set, DB input data MSB to LSB order is reversed, DB[15] = LSB and DB[0]= MSB. fir_bypass: When set, all interpolation filters are bypassed (interp(1:0) setting has no effect). QMC and NCO blocks are functional in this mode up to fDAC = 250 MHz, limited by the input data rate.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Register Name: CONFIG3—Address: 0x04, Default = 0x00 BIT 7 BIT 0 sif_4pin dac_ser_data half_rate unused usb 0 0 0 0 0 counter_mode(2:0) 0 0 0 sif_4pin: Four-pin serial interface mode is enabled when set, three-pin mode when cleared. dac_ser_data: When set, both DAC A and DAC B input data is replaced with fixed data loaded into the 16-bit serial interface ser_data register. half_rate: Enables half-rate input mode.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Register Name: SER_DATA_1—Address: 0x07, Default = 0x00 BIT 7 BIT 0 dac_data(15:8) 0 0 0 0 0 0 0 0 dac_data(15:8): Upper 8 bits of DAC data input to the DACs when dac_ser_data is set. Register Name: BYPASS_MASK_CNTL—Address: 0x08, Default = 0x00 BIT 7 BIT 0 fast_latch bp_ invsinc bp_fir3 bp_qmc bp_fmix bp_fir2 bp_fir1 nco_only 0 0 0 0 0 0 0 0 These modes are for factory use only – leave as default.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Register Name: NCO_PHASE_1—Address: 0x0E, Default = 0x00 BIT 7 BIT 0 phase(15:8) 0 0 0 0 0 0 0 0 phase(15:8): Bits 15:8 of the NCO phase offset word. Register Name: DACA_OFFSET_0—Address: 0x0F, Default = 0x00 BIT 7 BIT 0 daca_offset(7:0) 0 0 0 0 0 0 0 0 daca_offset(7:0): Bits 7:0 of the DAC A offset word.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Register Name: QMCB_GAIN_0—Address: 0x14, Default = 0x00 BIT 7 BIT 0 qmc_gain_b(7:0) 0 0 0 0 0 0 0 0 qmc_gain_b(7:0): Bits 7:0 of the QMC B path gain word. Updates to this register do not take effect until DACA_OFFSET_0 has been written. Register Name: QMC_PHASE_0—Address: 0x15, Default = 0x00 BIT 7 BIT 0 qmc_phase(7:0) 0 0 0 0 0 0 0 0 qmc_phase(7:0): Bits 7:0 of the QMC phase word.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Register Name: DAC_CLK_CNTL—Address: 0x1A, Default = 0x00 BIT 7 BIT 0 Factory use only 0 0 0 0 0 0 0 0 Reserved for factory use only. Register Name: ATEST—Address: 0x1B, Default = 0x00 BIT 7 BIT 0 atest(4:0) 0 0 phstr_del(1:0) 0 0 0 0 unused 0 0 atest(4:0): Can be used to enable clock output at the PLLLOCK pin according to Table 5. Pin EXTLO must be open when atest(4:0) is not equal to 00000. Table 5.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Serial Interface The serial port of the DAC5687 is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of the DAC5687. It is compatible with most synchronous transfer formats and can be configured as a three- or four-pin interface by sif_4pin in register CONFIG3.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Instruction Cycle SDENB Data Transfer Cycle(s) SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ts(SDENB) t(SCLK) SDENB SCLK SDIO ts(SDIO) t(SCLKL) th(SDIO) t(SCLKH) T0037-02 Figure 33. Serial-Interface Write Timing Diagram Figure 34 shows the serial interface timing diagram for a DAC5687 read operation. SCLK is the serial interface clock input to the DAC5687.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 FIR Filters Figure 35 shows the magnitude spectrum response for the identical 51-tap FIR1 and FIR3 filters. The transition band is from 0.4 to 0.6 × fIN (the input data rate for the FIR filter) with < 0.002-dB pass-band ripple and > 80-dB stop-band attenuation. Figure 36 shows the region from 0.35 to 0.45 × fIN. Up to 0.44 × fIN, there is less than 0.5 dB of attenuation.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 20 4 0 3 FIR4 2 −40 Magnitude – dB Magnitude – dB −20 −60 −80 −100 1 Corrected 0 −1 −2 −120 Sin(x)/x −140 −3 −160 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 −4 0.0 f/fIN 0.1 0.2 0.3 0.4 fOUT/fDAC G048 Figure 37. Magnitude Spectrum for FIR2 0.5 G049 Figure 38. Magnitude Spectrum for Inverse Sinc Filter FIR4 (Versions 1 and 2) Table 8.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Dual-Channel Real Upconversion The DAC5687 can be used in a dual-channel mode with real upconversion by mixing with a 1, –1, … sequence in the signal chain to invert the spectrum. This mixing mode maintains isolation of the A and B channels. There are two points of mixing: in X4L mode, the FIR1 output is inverted (high-pass mode) by setting registers hpla and hplb to 1, and the FIR3 output is inverted by setting CMIX to fDAC/2.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Synchronization of the NCO occurs by resetting the NCO accumulator to zero with assertion of PHSTR. See the following NCO Synchronization section. Frequency word freq in the frequency register is added to the accumulator every clock cycle. The output frequency of the NCO is (freq * 2 32) f NCO_CLK freq f NCO_CLK 31 f NCO + for freq v 2 f + for freq u 2 31 NCO 2 32 2 32 ń where fNCO_CLK is the clock frequency of the NCO circuit.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Table 10.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 qmc_gain_a/210 {0, 1/210, ..., 2 – 1/210} 11 I(t) Σ X 10 X Q(t) X qmc_phase/210 {–1/2, –1/2 + 1/210, ..., 1/2 – 1/210} 11 qmc_gain_b/210 {0, 1/210, ..., 2 – 1/210} B0164−01 Figure 40. QMC Block Diagram LO LO sideband sideband Uncorrected Corrected C003 Figure 41.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 During the four DAC clock cycles, the partially updated offset register values are summed to the DAC signal. This can result in offset values during the first three DAC clock cycles that are significantly different from the starting and ending offset values. For example, Table 11 shows the transition from offset value 1023 to 1025. The bit changes in each clock cycle are in bold.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 1. PLLVDD = 0 V and dual_clk = 0: EXTERNAL CLOCK MODE In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used. The LPF and CLK1/CLK1C pins can be left unconnected. The input data-rate clock and interpolation rate are selected by the bits interp(1:0) in register CONFIG0 and is output through the PLLLOCK pin.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 A type-four phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated by dividing the VCO output by 1×, 2×, 4×, or 8× as selected by the prescaler div(1:0). The output of the prescaler is the DAC sample rate clock and is divided down to generate clocks at ÷2, ÷4, and ÷8.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 3. PLLVDD = 0 V and dual_clk = 1: DUAL CLOCK MODE In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and the input data rate through CLK1/CLK1C. There are two options in dual clock mode: with FIFO (inv_plllock set) and without FIFO (inv_plllock clear). If the FIFO is not used, the CLK1/CLK1C input is used to set the phase of the internal clock divider.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 2 – 16 y fDATA fDATA FIR1 2fDATA ••• 16-Bit DAC IOUTA1 16-Bit DAC IOUTB1 IOUTA2 y2 DEMUX DA[15:0] Edge Triggered Input Latches 2fDATA ••• IOUTB2 y2 B0025-02 Figure 49. Interleave Bus Mode Data Path TXENABLE ts(TXENABLE) CLK1 or PLLLOCK ts(DATA) th(DATA) DA[15:0] A0 B0 A1 B1 AN BN T0041-01 Figure 50.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 When using interleaved input mode with the PLL enabled, input clock CLK1 is at 2× the frequency of the input to FIR1. If the dividers for multiple DAC5687s are not synchronized, there can be a one-CLK1-period output time difference between devices that have synchronized input data. However, the divider that generates the clock for the FIR1 input is not connected to the DAC5687 synchronization circuitry.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Initialization of the FIFO block involves selecting and asserting a synchronization source. Initialization causes the input and output pointers to be forced to an offset of 2; the input pointer is forced to the in_sel_a state, while the output pointer is forced to the sel_q_c state. This initialization of the input and output pointers can cause discontinuities in a data stream and should therefore be handled at startup. Table 12.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Once initialized, the FIFO input pointer advances using clk_in and the output pointer advances using clk_out, providing an elastic buffering effect. The phase relationship between clk_in and clk_out can wander or drift until the output pointer overruns the input pointer or vice versa. Even/Odd Input Mode The DAC5687 has a double data rate input mode that allows both input ports to be used to multiplex data onto one DAC channel (A).
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 PHSTR D Q D Q PHSTR Sync to NCO D Q D Q D Q DQ Phase Accumulator Reset FIFO MUX clk_nco PLLLOCK clk_out PLL VCO Clock Generator clk_in CLK2 CLK2C CLK1 CLK1C {PLLVDD, inv_plllock, dual_clk} B0168-01 Figure 54. Logic Path for PHSTR Synchronization Signal to NCO The serial interface includes a sync_nco bit in register SYNC_CNTL, which must be set for the PHSTR input signal to initialize the phase accumulator.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Coarse Mixer (CMIX) Synchronization The coarse mixer implements the fDAC/2 and fDAC/4 (and –fDAC/4) fixed complex mixing operation using simple complements of the data-path signals to create the proper sequences. The sequences are controlled using a simple counter, and this counter can be synchronously reset using the PHSTR signal. Similar to the NCO, the PHSTR signal used by the coarse mixer is from the FIFO output.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Only Must Be High for One clk_in Period PHSTR clk_in Input Delay Line + FIFO Delay clk_out phstr at FIFO Output clk_cmix Sequencer Reset Sequencer fs/2 0 180 Sequencer fs/4 0 90 0 180 180 270 0 90 T0155-01 Figure 57. CMIX Reset Synchronization Timing In addition to the reset function provided by the PHSTR signal, the phstr_del(1:0) bits in register ATEST allow the user to select the initial (reset) state.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Ref CDC7005 #1 fINPUT Ref CDC7005 #2 Y0 Y0 fINPUT CLK1 CLK1C Y1 Y1 fDAC CLK2 CLK2C Y2 Y2 fINPUT CLK1 CLK1C Y3 Y3 fDAC CLK2 CLK2C Y0 Y0 fINPUT CLK1 CLK1C Y1 Y1 fDAC CLK2 CLK2C Y2 Y2 fINPUT CLK1 CLK1C Y3 Y3 fDAC CLK2 CLK2C DAC5687 #1 DAC5687 #2 DAC5687 #3 DAC5687 #4 B0170-01 Figure 58.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 The full-scale output current is set using external resistor RBIAS in combination with an on-chip band-gap voltage reference source (1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to provide a full-scale output current equal to 16 times IBIAS. The full-scale current IOUTFS can be adjusted from 20 mA down to 2 mA.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 AVDD RLOAD RLOAD IOUT1 IOUT2 S(1) S(1)C S(2) S(2)C S(N) S(N)C S0032-01 Figure 59. Equivalent Analog Current Output The DAC5687 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF transformer. Figure 60 and Figure 61 show the 50-Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 AVDD (3.3 V) 100 Ω 4:1 IOUT1 RLOAD 50 Ω IOUT2 100 Ω AVDD (3.3 V) S0033-02 Figure 61. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer Combined Output Termination The DAC5687 DAC A and DAC B outputs can be summed together as shown in Figure 62 to provide a 40-mA full-scale output for increased output power. 1:1 IOUTA1 RLOAD 50 Ω IOUTA2 IOUTB1 AVDD (3.3 V) IOUTB2 S0069-01 Figure 62.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 QOUT(t) = (IIN(t)sin(2π × 0 × t + π/4) + 0 × cos(2π × 0 × t + π/4)) × 2(1 – 1) = IIN(t)sin(π/4) = IIN(t)/2½ Applying the QMC gain of 1446, equivalent to 2½, increases the signal back to unity gain through the FMIX and the QMC blocks. Note that with this termination, the DAC side of the transformer is not 50-Ω terminated and therefore may result in reflections when used with a cable output.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Optional, May Be Bypassed for Sine Wave Input Swing Limitation CAC 0.1 µF 1:4 CLK RT 200 Ω CLKC Termination Resistor S0029-01 Figure 65. Clock Input Configuration Using 50-Ω Cable Input Ropt 22 Ω CAC 0.01 µF Ropt 22 Ω 1:1 TTL/CMOS Source TTL/CMOS Source CLK Optional, Reduces Clock Feedthrough CLKC CLK CLKC 0.01 µF Node CLKC Internally Biased to CLKVDDń2 S0030-01 Figure 66.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Power-Up Sequence In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or simultaneously with PLLVDD. AVDD, CLKVDD, and IOVDD can be powered simultaneously or in any order. Within AVDD, the multiple AVDD pins should be powered simultaneously. There are no specific requirements on the ramp rate for the supplies.
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DAC5687 www.ti.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 GND 5V 205 Ω 205 Ω 50 Ω 50 Ω 15.4 Ω 15.4 Ω TRF3701 TRF3702 15.4 Ω 15.4 Ω 205 Ω 205 Ω 50 Ω 50 Ω 5V GND B0046-01 Figure 68. DAC5687 Passive Interface to TRF3701/2 Analog Quadrature Modulator Changing the voltage levels and resistor values enables other common-mode voltages at the analog quadrature modulator input. For example, the network shown in Figure 69 can produce a 3.3-V common mode for the TRF3703-33, with a 0.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 To calculate the nonharmonic clock-related spurious signals for a particular condition, we first determine the location of the spurious signals and then the amplitude.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 (a) Complex Output in X4 and X4L Modes (b) Real Output in X4 and X4L Modes 0.5 0.4 0.50 fSIG + fDAC/4 fSIG − fDAC*3/4 0.40 fSIG 0.2 Spurious Frequency/fDAC Spurious Frequency/fDAC 0.3 0.1 fSIG − fDAC/4 0.0 −0.1 fSIG − fDAC/2 −0.2 −0.3 0.35 fSIG 0.30 0.25 fSIG − fDAC/4 0.20 fSIG − fDAC/2 0.15 0.10 fSIG − fDAC*3/4 −0.4 −0.5 0.0 fSIG + fDAC/4 0.45 0.1 0.2 0.05 0.3 0.4 fSIG/fDAC 0.00 0.0 0.5 0.1 0.2 0.3 0.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Figure 73 and Figure 74 show the typical worst-case spurious signal amplitudes vs fDAC for a signal frequency fSIG = 11 × fDAC/32 in each mode for PLL on (PLL clock mode) and PLL off (external and dual-clock modes). Each spurious signal (fDAC/2, fDAC/4 and fDAC/8) has its own curve. The spurious signal amplitudes can then be adjusted for the exact signal frequency fSIG by applying the amplitude adjustment factor shown in Figure 75.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 40 Amplitude Adjustment − dB 30 20 10 0 −10 −20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 fSIG/fDAC G040 Figure 75. Amplitude Adjustment Factor for fSIG The steps for calculating the nonharmonic spurious signals are: 1. Find the spurious signal frequencies for the appropriate mode from Figure 70, Figure 71, or Figure 72. 2. Find the amplitude for each spurious frequency for the appropriate mode from Figure 73 or Figure 74. 3.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 First, the location of the spurious signal is found for the X2 real output in Figure 70(b). One spurious signal is present in the range 0 to 0.5 × fDAC at 0.325 × fDAC (see Table 17). Consulting Figure 74(a), the raw amplitude for fDAC/2 is 47 dBc. From Figure 75, the amplitude adjustment factor for fSIG = 0.175 × fDAC is estimated at ~6 dB, and so the fDAC/2 spurious signal is adjusted to 53 dBc. Table 17.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 DAC5687 DUC I y2 y2 NCO RF Processing DAC DUC TRF3750 Q y2 y2 GC4116 GC5016 GC5316 CDC7005 B0040-01 Figure 76.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 DAC5687 RF Processing DUC Ch2 DAC y2 DUC y2 1, −1, 1, ... 1, −1, 1, ... RF Processing DUC Ch1 DAC y2 DUC y2 GC4116 GC5016 GC5316 TRF3750 CDC7005 B0041-01 Figure 77. System Diagram of a Dual-Channel Real IF Radio The outputs of multiple DAC5687s can be phase synchronized for multiple antenna/beamforming applications.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 A(t) = I(t)cos(ωct) – Q(t)sin(ωct) = m(t) B(t) = I(t)sin(ωct) + Q(t)cos(ωct) = mh(t) where m(t) and mh(t) connote a Hilbert transform pair and ωc is the sum of the NCO and CMIX frequencies. The complex DAC5687 output is input to an analog quadrature modulator (AQM) such as the TRF3701 or TRF3702. A passive (resistor-only) interface is recommended between the DAC5687 and TRF3701/2 (See the Passive Interface to TRF3701/2 section).
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Table 18. Signal and System Properties for Complex IF System Example in Figure 79 Signal Three WCDMA carriers, test model 1 Baseband carrier offsets –7.5 MHz, 2.5 MHz, 7.5 MHz DAC5687 input rate 122.88 MSPS DAC5687 output rate 491.52 MSPS (4× interpolation) DAC5687 mode X4 CMIX DAC5687 complex IF 122.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Application Example: CMTS/VOD Transmitter The exceptional SNR of the DAC5687 enables a dual-cable modem termination system (CMTS) or video on demand (VOD) QAM transmitter in excess of the stringent DOCSIS specification, with > 74 dBc and 75 dBc in the adjacent and alternate channels. A typical system using the DAC5687 for a cost-optimized dual-channel two-QAM transmitter is shown in Figure 81.
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 C002 Figure 82. Two QAM256 Carriers With 36-MHz IF Application Example: High-Speed Arbitrary Waveform Generator The DAC5687 flexible input allows use of the dual input ports with demultiplexed odd/even samples at a combined rate of up to 500 MSPS. Combined with the DAC 16-bit resolution, the DAC5687 allows wideband signal generation for test and measurement applications.
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DAC5687 SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 www.ti.com Changes from Revision D (July 2006) to Revision E ...................................................................................................... Page • • Inverted CLK2 waveform in Figure 50 timing diagram ....................................................................................................... 44 Deleted Δ < talign from Figure 51 timing diagram........................................................................
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DAC5687 www.ti.com SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 Changes from Revision B (June 2005) to Revision C .................................................................................................... Page • • • • • • • • • • • • • First sentence: Changed "The lower limit" to "upper limit". 3rd sentence: "upper limit" to "lower limit". Last sentence: "Exceeding the upper limit" to "Exceeding the limits". ..................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC5687IPZPR Package Package Pins Type Drawing HTQFP PZP 100 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 17.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 17.0 1.5 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5687IPZPR HTQFP PZP 100 1000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.