Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VQFN 64

DAC5688

www.ti.com

SLLS880C –DECEMBER 2007–REVISED AUGUST 2010

DUAL-CHANNEL, 16-BIT, 800 MSPS, 2x–8x INTERPOLATING

DIGITAL-TO-ANALOG CONVERTER (DAC)

Check for Samples: DAC5688

FEATURES

DESCRIPTION

• Dual, 16-Bit, 800 MSPS DACs

The DAC5688 is a dual-channel 16-bit 800 MSPS

digital-to-analog converter (DAC) with dual CMOS

• Dual, 16-Bit, 250 MSPS CMOS Input Data

digital data bus, integrated 2x-8x interpolation filters,

– 16 Sample Input FIFO

a fine frequency mixer with 32-bit complex

– Flexible input data bus options

numerically controlled oscillator (NCO), on-board

• High Performance clock multiplier, IQ compensation, and internal

voltage reference. Different modes of operation

– 81 dBc ACLR WCDMA TM1 at 70 MHz

enable or bypass various signal processing blocks.

• 2x-32x Clock Multiplying PLL/VCO

The DAC5688 offers superior linearity, noise,

• Selectable 2x–8x Interpolation Filters

crosstalk and PLL phase noise performance.

– Stop-band Attenuation > 80 dB

The DAC5688 dual CMOS data bus provides 250

• Complex Mixer with 32-Bit NCO MSPS input data transfer per DAC channel. Several

input data options are available: dual-bus data,

• Digital Quadrature Modulator Correction

single-bus interleaved data, even and odd

– Gain, Phase and Offset Correction

multiplexing at half-rate, and an input FIFO with either

• Digital Inverse SINC Filter

external or internal clock to ease interface timing.

Input data can interpolated 2x, 4x or 8x by on-board

• 3- or 4-Wire Serial Control Interface

digital interpolating FIR filters with over 80 dB of

• On Chip 1.2-V Reference

stop-band attenuation.

• Differential Scalable Output: 2 to 20 mA

The DAC5688 allows both complex or real output. An

• Package: 64-pin 9×9mm QFN

optional 32-bit NCO/mixer in complex mode provides

frequency upconversion and the dual DAC output

APPLICATIONS

produces a complex Hilbert Transform pair. A digital

Inverse SINC filter compensates for natural DAC

• Cellular Base Stations

sin(x)/x frequency roll-off. The digital Quadrature

• Broadband Wireless Access (BWA)

Modulator Correction (QMC) feature allows IQ

• WiMAX 802.16

compensation of phase, gain and offset to maximize

• Fixed Wireless Backhaul

sideband rejection and minimize LO feed-through of

• Cable Modem Termination System (CMTS)

an external quadrature modulator performing the final

single sideband RF up-conversion.

The DAC5688 is pin compatible with the DAC5689

which does not include a clock-multiplying PLL. The

DAC5688 is characterized for operation over the

industrial temperature range of –40°C to 85°C and is

available in a 64-pin 9x9mm QFN package.

ORDERING INFORMATION

(1)

Order Code Package Qty Package

= –40°C to 85°C Tape and Reel Format Drawing/Type

(2) (3)

DAC5688IRGCT 250

RGC / 64QFN Quad Flatpack No-Lead

DAC5688IRGCR 2000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Thermal Pad Size: 7,4 mm × 7,4 mm

(3) MSL Peak Temperature: Level-3-260C-168 HR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (56 pages)

PAGE 1
DAC5688 www.ti.
PAGE 2
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 PIN FUNCTIONS PIN NAME NO. I/O DESCRIPTION AVDD 51, 54, 55, 59, 62 I Analog supply voltage. (3.3V) BIASJ 57 O Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND. CLK2 2 I With the clock multiplier PLL enabled, CLK2 provides lower frequency reference clock. If the PLL is disabled, CLK2 directly provides clock for DAC up to 800 MHz. CLK2C 3 I Complementary CLK2 input.
PAGE 4
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.5 to 2.3 V –0.5 to 2.3 V –0.5 to 2.3 V AVDD (2) –0.5 to 4 V IOVDD (2) –0.5 to 4 V DVDD (2) Supply Voltage Range VFUSE (2) CLKVDD (2) Supply Voltage Range AVDD to DVDD –2 to 2.6 V CLKVDD to DVDD –0.5 to 0.5 V IOVDD to AVDD –0.5 to 0.5 V –0.5 to CLKVDD + 0.5 V –0.5 to IOVDD + 0.5 V –0.5 to IOVDD + 0.
PAGE 5
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, DVDD, CLKVDD = 1.8 V, IOUTFS = 20 mA PARAMETER TEST CONDITIONS RESOLUTION MIN TYP MAX UNIT 16 Bits DC ACCURACY INL Integral nonlinearity DNL Differential nonlinearity 1 LSB = IOUTFS/216 ±4 LSB ±2 LSB ANALOG OUTPUT Coarse gain linearity ± 0.
PAGE 6
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, DVDD, CLKVDD = 1.8 V, IOUTFS = 20 mA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT (1) fDAC Maximum output update rate ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF tpd Output propagation delay DAC outputs are updated on falling edge of DAC clock.
PAGE 7
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, DVDD, CLKVDD = 1.8V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB, DA[15:0], DB[15:0], SYNC, TXENABLE, CLKO_CLK1, LOCK_CLK1C CONFIG26 io_1p8_3p3 = 0 (3.3V levels) 2.30 CONFIG26 io_1p8_3p3 = 1 (1.8V levels) 1.
PAGE 8
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, DVDD, CLKVDD = 1.8V.
PAGE 9
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS Figure 1. Integral Nonlinearity Figure 2. Differential Nonlinearity vertical spacer vertical spacer vertical spacer Figure 3. Single Tone Spectral Plot Figure 4.
PAGE 10
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 85 Fdata = 200 MSPS FIN = 10.1 MHz, Sweep FMIX x4 Interpolation PLL off 80 SFDR - dBc 75 70 65 60 55 50 Figure 5. In-Band SFDR vs. Intermediate Frequency 100 150 200 FOUT (MHz) 250 300 350 0 Fdata = 200 MSPS IF = FNCO x4 Interpolation, PLL off 105 Fdata = 200 MSPS, IQ FIN = 20 MHz ±0.
PAGE 11
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) 85 0 Fdata = 200 MSPS, IQ FIN = 0 MHz IF = 140 MHz x4 Interpolation, FMIX PLL off -10 -20 80 -30 75 -40 ACLR - dBc Power - dBm Fdata = 92.16 MSPS IF = FNCO x8 Interpolation Fdac = 737.28 MSPS -50 -60 PLL OFF 70 65 -70 PLL ON -80 60 -90 -100 138 139 140 IF - MHz 141 142 55 50 0 100 150 200 IF (MHz) 250 300 350 Figure 9. Two Tone IMD Spectral Plot Figure 10.
PAGE 12
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 12 Figure 13. WCDMA TM1:Single Carrier, PLL Off Figure 14. WCDMA TM1:Single Carrier, PLL On vertical spacer vertical spacer vertical spacer Figure 15. WCDMA TM1:Two Carriers, PLL Off Figure 16.
PAGE 13
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Figure 17. WCDMA TM1:Four Carriers, PLL Off Figure 18.
PAGE 14
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com TEST METHODOLOGY Typical AC specifications were characterized with the DAC5688EVM. A sinusoidal master clock frequency is generated by an HP8665B signal generator which drives an Agilent 8133A pulse generator to generate a square wave output clock for the TSW3100 Pattern Generator and EVM input clock.
PAGE 15
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 REGISTER DESCRIPTIONS Table 1.
PAGE 16
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com Register name: STATUS0 - Address: 0x00, Default 0x01 Bit 7 Bit 6 Bit 5 PLL_lock 0 unused 0 unused 0 PLL_lock device_ID(2:0) version(1:0) : : : Bit 4 Bit 3 0 device_ID (2:0) 0 Bit 2 Bit 1 Bit 0 version(1:0) 0 0 1 Bit 1 Bit 0 Asserted when the internal PLL is locked. (Read Only) Returns ‘000’ for DAC5688. (Read Only) A hardwired register that contains the version of the chip.
PAGE 17
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 Register name: CONFIG2 Address: 0x02, Default 0xE1 Bit 7 Bit 6 Bit 5 Bit 4 diffclk_ena 1 clk1_in_ena 1 clk1c_ in_ena 1 clko_SE_hold 0 diffclk_ena : clk1_in_ena : clk1c_in_ena : clko_SE_hold : fir4_ena qmc_offset_ena qmc_corr_ena mixer_ena : : : : Bit 3 Bit 2 fir4_ ena 0 Bit 1 qmc_ offset_ena 0 qmc_ corr_ena 0 Bit 0 mixer_ena 1 When set (default), CLK1 and CLK1C pins are used as a differential clock input.
PAGE 18
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com Register name: CONFIG5 Address: 0x05, Default 0x22 Bit 7 sif4 0 Bit 6 sif_ sync_sig 0 sif4 sif_sync_sig clkdiv_sync_ena clkdiv_sync_sel clkdiv_shift : : : : : mixer_gain : Bit 5 Bit 4 clkdiv_sync_ena 1 clkdiv_sync_sel 0 Bit 3 Reserved 0 Bit 2 clkdiv_shift 0 Bit 1 mixer_gain 1 Bit 0 unused 0 When set, the serial interface (SIF) is a 4 bit interface, otherwise it is a 3 bit interface. SIF created sync signal.
PAGE 19
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 Register name: CONFIG11 Address: 0x0B, Default 0x00 (Synced) Bit 7 Bit 6 0 phaseadd(31:24) 0 : Bit 5 0 Bit 4 Bit 3 phaseadd(31:24) 0 0 Bit 2 Bit 1 Bit 0 0 0 0 The phaseadd(31:24) value is used to determine the frequency of the NCO. The two’s complement formatted value can be positive or negative and the LSB is equal to Fs/(2^32).
PAGE 20
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com Register name: CONFIG14 Address: 0x0E, Default 0x00 (Synced) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 qmc_phase(7:0) 0 0 qmc_phase(7:0) : 0 0 0 Lower 8 bits of the 10-bit Quadrature Modulator Correction (QMC) phase word. The upper 2 bits are in the CONFIG15 register. The full 11-bit qmc_phase(9:0) correction word is formatted as two’s complement and scaled to occupy a range of –0.125 to 0.
PAGE 21
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 Register name: CONFIG18 Address: 0x12, Default 0x00 (Synced) Bit 7 Bit 6 Bit 5 0 qmc_offseta(12:8) 0 0 qmc_offseta(12:8) Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0 0 unused 0 unused 0 unused 0 : Upper 5 bits of the DACA offset correction.
PAGE 22
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com Register name: CONFIG23 Address: 0x17, Default 0x15 Bit 7 Bit 6 unused 0 unused 0 fifo_sel(2:0) : Bit 5 Bit 4 0 fifo_sel(2:0) 1 : Bit 2 Bit 1 Bit 0 0 aflag_ sel 1 unused 0 unused 1 Selects the sync source for the FIFO from the table below.
PAGE 23
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 Register name: CONFIG27 Address: 0x1B, Default 0xFF Bit 7 Bit 6 Bit 5 Bit 4 coarse_daca(3:0) 1 1 1 coarse_daca(3:0) : : 1 1 Bit 2 Bit 1 coarse_dacb(3:0) 1 1 Bit 0 1 Scales the output current is 16 equal steps. V EXTIO Rbias coarse_dacb(3:0) Bit 3 (DACA_gain ) 1) Same as above except for DACB.
PAGE 24
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com Register name: CONFIG30 Address: 0x1E, Default 0x00 Bit 7 Bit 6 PLL_LPF_ reset 0 VCO_div2 0 PLL_LPF_reset VCO_div2 : : PLL_gain(1:0) : PLL_range(3:0) : 24 Bit 5 Bit 4 Bit 3 Bit 2 PLL_gain(1:0) 0 Bit 1 Bit 0 PLL_range(3:0) 0 0 0 0 0 When set, can be used to hold the PLL loop filter at 0 volts. When set, the PLL CLOCK output is 1/2 the PLL VCO frequency.
PAGE 25
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 DETAILED DESCRIPTION EXAMPLE SYSTEM DIAGRAM DAC5688 DAC DAC I-Signal Term InvSINC QMC (Gain/Phase) NCO/Mixer FIFO & Demux DB[15:0] 16 I/Q FIR1-3 (8x) DAC Antenna LPF 5V PA Q-Signal Term LPF To TX Feedback TXENABLE Clock, Sync & Control CLK1 90 opt. PLL CLK2 CLK2C Digital Up Converter (DUC) TRF3703 AQM 5V DA[15:0] 16 76.8 MHz Loop Filter To RX Path 0 ~ 2.1 GHz TRF3761- X PLL /VCO Div 1/2/4 100 CK 76.
PAGE 26
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com Table 2. Instruction Byte of the Serial Interface Bit Description R/W [N1 : N0] 7 6 5 4 3 2 1 0 R/W N1 N0 A4 A3 A2 A1 A0 Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from DAC5688 and a low indicates a write operation to DAC5688. Identifies the number of data bytes to be transferred per Table 3. Data is transferred MSB first. Table 3.
PAGE 27
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 Instruction Cycle SDENB Data Transfer Cycle(s) SCLK SDIO r/w N1 N0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 - D7 D6 D5 D4 D3 D2 D1 D0 0 SDO 4 pin configuration 3 pin configuration output output SDENB SCLK SDIO SDO Data n Data n-1 t d (Data) Figure 21. Serial Interface Read Timing Diagram FIR FILTERS Figure 22 shows the magnitude spectrum response for FIR1, a 67-tap interpolating half-band filter. The transition band is from 0.
PAGE 28
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com Magnitude Spectrum for FIR1 Magnitude Spectrum for FIR1 0.1 20 0 0 -20 -0.1 -40 dB dB -60 -80 -0.2 -0.3 -100 -0.4 -120 -0.5 -140 -160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.37 1.0 0.38 0.39 0.4 f/Fin Figure 22. Magnitude Spectrum for FIR1 0.41 0.42 f/Fin 0.43 0.44 0.45 0.46 0.47 Figure 23.
PAGE 29
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 8x Interpolation Composite Filtering Response Magnitude Spectrum for FIR 3 20 0 0 -20 -20 -40 -40 -60 dB dB -60 -80 -80 -100 -100 -120 -120 -140 -140 -160 0 -160 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.5 1 2 f/Fin 1 f/Fin Figure 26. Magnitude Spectrum for FIR3 vertical spacer vertical spacer 3 4 Figure 27. 8x Interpolation Composite Response FIR 4 Inverse Corrected Spectrum 5 4 3 2 dB 1 0 -1 -2 -3 -4 -5 0 0.
PAGE 30
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com Table 4.
PAGE 31
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 Full Complex Mixer (FMIX) The full complex Mixer (FMIX) block uses a Numerically Controlled Oscillator (NCO) with a 32-bit frequency register phaseadd(31:0) and a 16-bit phase register phaseoffset(15:0) to provide sin and cos for mixing. The NCO tuning frequency is programmed in CONFIG8 through CONFIG11 registers. Phase offset is programmed in CONFIG6 and CONFIG7 registers. A block-diagram of the NCO is shown below in Figure 29.
PAGE 32
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com Quadrature Modulator Correction (QMC) The Quadrature Modulator Correction (QMC) block provides a means for adjusting the gain and phase of the complex signal. At a quadrature modulator output, gain and phase imbalances result in an undesired sideband signal. The block diagram for the QMC is shown in Figure 30. The QMC block contains 3 programmable parameters: qmc_gaina(10:0), qmc_gainb(10:0) and qmc_phase(9:0).
PAGE 33
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 CLOCK MODES The DAC5688 supports several different clocking modes for generating the internal clocks for the logic and DAC. The clocking modes are selected by programming the register bits below and summarized in Table 5. Register Control Bits CONFIG1 synchr_clkin CONFIG2 clk1_in_ena, clk1c_in_ena, diffclk_ena CONFIG26 PLL_ena Table 5.
PAGE 34
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com EXTERNAL CLOCK MODE In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through CLK2/C. The CLKO_CLK1 pin is configured as an output in this mode and will toggle at a required frequency for the configured interpolation rate and data mode. The CLKO_CLK1 clock can be used to drive the input data source (such as digital upconverter) that sends the data to the DAC.
PAGE 35
DAC5688 (Pin 64) External Loop Filter LPF (3.3V, Pin 9) IOVDD (1.8V, Pin 1) SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 CLKVDD www.ti.
PAGE 36
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com INTERLEAVED BUS MODE In INTERLEAVED BUS MODE, the user inputs dual-channel data as an interleaved single data stream to either DA[15:] or DB[15:0] ports. The DAC5688 de-interleaves the input data stream and routes to both A and B data paths. For input data on DA[15:0], set CONFIG1 insel_mode[15:0] = ‘01’. For input data on DB[15:0], set CONFIG1 insel_mode[15:0] = ‘10’.
PAGE 37
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 CLK2 and CLK2C Inputs Figure 39 shows an equivalent circuit for the DAC input clock (CLK2/C). CLKVDD 333 W CLK2 2 KW Note: Input common mode level is approximately 2/3 * CLKVDD or 1.2 V. 2 KW CLK2C 666 W GND Figure 39. CLK2/C Equivalent Input Circuit Figure 40 shows the preferred configuration for driving the CLK2/CLK2C input clock with a differential ECL/PECL source. 0 .
PAGE 38
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com CLKO_CLK1 and LOCK_CLK1C Pins Figure 41 shows the functionality of the CLKO_CLK1 and LOCK_CLK1C pins. Refer to Table 5. The controls for these pins are found in the CONFIG2 register and are used in selection of device clocking mode. In single-ended mode (CONFIG2 diffclk_ena = ‘0’) refer to Figure 43, both CLKO_CLK1 and LOCK_CLK1C pins have an internal pull-down resistor approximately equivalent to 100kΩ.
PAGE 39
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 CMOS DIGITAL INPUTS Figure 43 shows a schematic of the equivalent CMOS digital inputs of the DAC5688. SDIO, SCLK, SYNC, TXENABLE, DA[15:0] and DB[15:0] have pull-down resistors while RESETB and SDENB have pull-up resistors internal the DAC5688. See specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ. The input switches levels for all CMOS digital inputs can be changed from 3.
PAGE 40
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage reference source (+1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to provide a maximum full-scale output current equal to 16 times IBIAS.
PAGE 41
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 ANALOG CURRENT OUTPUTS Figure 45 shows a simplified schematic of the current source array output with corresponding switches. Differential switches direct the current of each individual NMOS current source to either the positive output node IOUT1 or its complementary negative output node IOUT2.
PAGE 42
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com AVDD (3 .3 V ) 50 W 1:1 IOUT 1 RLOAD 100 W 50 W IOUT 2 50 W AVDD (3.3 V) Figure 46. Driving a Doubly Terminated 50Ω Cable Using a 1:1 Impedance Ratio Transformer AVDD (3 .3 V ) 100 W 4:1 IOUT 1 RLOAD 50 W IOUT 2 100 W AVDD (3.3 V) Figure 47.
PAGE 43
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 Vin ~ Varies Vout ~ 2.8 to 3.8 V I1 Signal Conditioning IOUTA1 IOUTA2 IOUTB1 IOUTB2 I2 S Q1 RF Q2 Quadrature modulator Figure 48. DAC to Analog Quadrature Modulator Interface The DAC5688 has a maximum 20mA full-scale output and a voltage compliance range of AVDD ± 0.5 V. The TRF3703 IQ modulator family can be operated at three common-mode voltages: 1.5V, 1.7V, and 3.3V.
PAGE 44
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com V1 R1 I I R3 DAC5688 TRF3703-33 V2 R3 /I /I R1 V1 Figure 50. DAC5688 to TRF3703-33 Interface In most applications a baseband filter is required between the DAC and the modulator to eliminate the DAC images. This filter can be placed after the common-mode biasing network. For the DAC to modulator network shown in Figure 51, R2 and the filter load R4 need to be considered into the DAC impedance.
PAGE 45
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 RECOMMENDED STARTUP SEQUENCE The following startup sequence is recommend to initialization the DAC5688: 1. Supply all 1.8V (CLKVDD, DVDD, VFUSE) and 3.3V (AVDD and IOVDD) voltages. 2. Toggle RESETB pin for a minimum 25 nSec active low pulse width. 3. Provide a stable CLK2/C input clock. 4. Program all desired SIF registers. 5. Provide a sync signal to all digital blocks.
PAGE 46
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com An Excel spreadsheet is provided by Texas Instruments for automatically calculating the values for C1, R1 and C2. DAC5688 PLL PLL LPF Pin 64 R1 C2 C1 External Loop Filter Figure 52.
PAGE 47
DAC5688 www.ti.com SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 REVISION HISTORY NOTE: Page numbers of previous versions may differ from current version. Changes from Revision A (March 2008) to Revision B Page • Changed Dual-Channel to first of title ................................................................................................................................... 1 • Changed sin(x)/x from upper case to lower case .....................................................................
PAGE 48
DAC5688 SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010 www.ti.com • Changed Figure 36 , Figure 37, Figure 38, caption from "......(PLL Clock Mode)" to "......(Dual Clock Mode)" ................. 35 • Changed graphic entity for Figure 40 ................................................................................................................................. 37 • Added section "PASSIVE INTERFACE TO ANALOG QUADRATURE MODULATORS." .................................................
PAGE 49
PACKAGE OPTION ADDENDUM www.ti.
PAGE 50
PACKAGE OPTION ADDENDUM www.ti.
PAGE 51
PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC5688IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 DAC5688IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.
PAGE 52
PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5688IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 DAC5688IRGCT VQFN RGC 64 250 336.6 336.6 28.
PAGE 53
PAGE 54
PAGE 55
PAGE 56
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.