Datasheet
DAC5688
SLLS880C –DECEMBER 2007–REVISED AUGUST 2010
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Register name: CONFIG14 Address: 0x0E, Default 0x00 (Synced)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
qmc_phase(7:0)
0 0 0 0 0 0 0 0
qmc_phase(7:0) : Lower 8 bits of the 10-bit Quadrature Modulator Correction (QMC) phase word. The upper 2 bits are in the
CONFIG15 register. The full 11-bit qmc_phase(9:0) correction word is formatted as two’s complement and
scaled to occupy a range of –0.125 to 0.12475 and a default phase correction 0.00. To accomplish QMC phase
correction, this value is multiplied by the current ‘Q’ sample, then summed into the ‘I’ sample. Refer to formatting
reference below.
qmc_phase(9:0) qmc_phase(9:0) Format Phase
[Binary] [Decimal] Correction
10000000000 –512 (–1 + 0/512) / 8 = –0.1250000
10000000001 –511 (–1 + 1/512) / 8 = –0.1234559
….. ….. ….
11111111111 –1 (–1 + 511/512) / 8 = –0.0002441
00000000000 [Default] 0 (+0 + 0/512) / 8 = +0.0000000
00000000001 1 (+0 + 1/512) / 8 = +0.0002441
….. ….. ….
01111111111 511 (+0 + 511/512) / 8 = +0.1247559
Register name: CONFIG15 Address: 0x0F, Default 0x24 (Synced)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
qmc_phase(9:8) qmc_gaina(10:8) qmc_gainb(10:8)
0 0 1 0 0 1 0 0
qmc_phase(9:8) : Upper 2 bits of qmc_phase term. Defaults to zero.
qmc_gaina(10:8) : Upper 3 bits of qmc_gaina term. Defaults to unity gain.
qmc_gainb(10:8) : Upper 3 bits of the qmc_gainb term. Defaults to unity gain.
Register name: CONFIG16 Address: 0x10, Default 0x00 (Synced)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
qmc_offseta(7:0)
0 0 0 0 0 0 0 0
qmc_offseta(7:0) : Lower 8 bits of the DACA offset correction. The upper 5 bits are in CONFIG18 register. The offset is
measured in DAC LSBs.
Register name: CONFIG17 Address: 0x11, Default 0x00 (Synced)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
qmc_offsetb(7:0)
0 0 0 0 0 0 0 0
qmc_offsetb(7:0) : Lower 8 bits of the DACB offset correction. The upper 5 bits are in
CONFIG19 register. The offset is measured in DAC LSBs.
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