Datasheet

DAC5688
SLLS880C –DECEMBER 2007–REVISED AUGUST 2010 www.ti.com
Register name: CONFIG23 Address: 0x17, Default 0x15
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
unused unused fifo_sel(2:0) aflag_ sel unused unused
0 0 0 1 0 1 0 1
fifo_sel(2:0) : Selects the sync source for the FIFO from the table below. For the case where the sync is dependent on the first
transition of the input data MSB: Once the transition occurs, the only way to get another sync it to reset the device
or to program fifo_sel to another value
fifo_sel (2:0) Sync selected
000 TXENABLE from pin
001 SYNC from pin
010 sync_SIF_sig (via CONFIG5)
011 Always zero
100 1
st
transition on DA MSB
101 1
st
transition on DB MSB
110 Always zero
111 Always one
aflag_sel : When set, the MSB of the input opposite of incoming data is used to determine the A sample. When cleared,
rising edge of TXENABLE is used. Refer to Figure 37.
Register name: CONFIG24 Address: 0x18, Default 0x80
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
fifo_sync_strt(3:0) Unused Unused Unused Unused
1 0 0 0 0 0 0 0
fifo_sync_strt(3:0) : When the sync to the FIFO occurs, this is the value loaded into the FIFO output position counter. With this
value the initial difference between input and output pointers can be controlled. This may be helpful in
syncing multiple chips or controlling the delay through the device.
Register name: CONFIG25 Address: 0x19, Default 0x00
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Unused Unused Unused Unused Unused Unused Unused Unused
0 0 0 0 0 0 0 0
Register name: CONFIG26 Address: 0x1A, Default 0x0D
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
io_1p8_3p3 Unused sleepb sleepa isbiaslpfb_a isbiaslpf_b PLL_ sleep PLL_ena
0 0 0 0 1 1 0 1
io_1p8_3p3 : Used to program the digital input voltage threshold levels. ‘0’=3.3V tolerate pads and ‘1’=1.8V tolerate pads.
Applies to following digital pins: CLKO_CLK1, LOCK_CLK1C, DA[15:0], DB[15:0], SYNC, RESETB, SCLK,
SDENB, SDIO (input only) and TXENABLE.
sleepb : When set, DACB is put into sleep mode. Putting the DAC into single DAC mode does not automatically assert this
signal, so for minimum power in single DAC mode, also program this register bit.
sleepa : When set, DACA is put into sleep mode. Note: If DACA channel is in sleep mode (sleepa = '1') the DACB channel
is also forced in to sleep mode.
isbiaslpfb_a : Turns on the low pass filter for the current source bias in the DACA when cleared. The low pass filter will set a
corner at ~472kHz when low and ~95 kHz when high.
isbiaslpfb_b : Turns on the low pass filter for the current source bias in the DACB when cleared. The low pass filter will set a
corner at ~472kHz when low and ~95 kHz when high.
PLL_sleep : When set, the PLL is put into sleep mode. Bypassing the PLL does not automatically but it into sleep mode.
PLL_ena : When set, the PLL is on and its output clock is being used as the DAC clock.
22 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5688