Datasheet
VCO
N-
Divider
Charge
Pump
R-
Div
Status& Control
PFD
10 MHz
REF
OSC
REF_IN
CPOUT
VCTRL_IN
90
0
TRF3703 AQM
DAC
DAC
LPF
NCO/Mixer
I/Q FIR1-3
(8x)
CLK2
opt.
PLL
Loop
Filter
100
DAC5688 DAC
PLL
Synth
TRF3761-XPLL/VCO
Loop
Filter
÷1÷8
Status &
Control
VCXO
CLK2C
Loop
Filter
Div
1/2/4
Clock Divider /
Distribution
CDCM7005
5V
5V
614.4 MHz
76.8 MHz
614.4 MHz
~ 2.1 GHz
Term
CLK1
DA[15:0]
GC5016
PA
Duplex er
Antenna
ToTX
Feedback
ToRX
Path
LPF
I-Signal
Q-Signal
Term
Term
TXENABLE
QMC
(Gain/Phase)
InvSINC
FIFO &
Demux
Clock, Sync & Control
÷8
76.8 MHz
CK
Digital
Up
Converter
(DUC)
DB[15:0]
16
16
DAC5688
www.ti.com
SLLS880C –DECEMBER 2007–REVISED AUGUST 2010
DETAILED DESCRIPTION
EXAMPLE SYSTEM DIAGRAM
Figure 19. Example System Diagram: Direct Conversion with 8x interpolation
SERIAL INTERFACE
The serial port of the DAC5688 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of DAC5688. It is compatible with most synchronous transfer formats and can be configured as
a 3 or 4 pin interface by SIF4 in register CONFIG5. In both configurations, SCLK is the serial interface input
clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in
and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input into the device
with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,
depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which
identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to
transfer the data. Table 2 indicates the function of each bit in the instruction cycle and is followed by a detailed
description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.
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