Datasheet

CLK 2

CLKO _ CLK 1

(output )

d(CLKO)

DA [0 : 15 ]

DB [0 : 15 ]

CLK0_CLK1

(inputoroutput)

DA [0 :15 ]

DB [0 :15 ]

DAC5688

SLLS880C –DECEMBER 2007–REVISED AUGUST 2010

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EXTERNAL CLOCK MODE

In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through CLK2/C.

The CLKO_CLK1 pin is configured as an output in this mode and will toggle at a required frequency for the

configured interpolation rate and data mode. The CLKO_CLK1 clock can be used to drive the input data source

(such as digital upconverter) that sends the data to the DAC. Note that the CKO_CLK1 delay relative to the input

CLK2 rising edge (t

d(CLKO

) in Figure 33) will increase with increasing loads.

Figure 33. EXTERNAL CLOCK MODE Timing Diagram

PLL CLOCK MODE

In PLL CLOCK MODE, the user provides an external reference clock to the CLK2/C input pins. Refer to

Figure 34. An internal clock multiplying PLL uses the lower-rate reference clock to generate a high-rate clock for

the DAC. This function is very useful when a high-rate clock is not already available at the system level;

however, the internal VCO phase noise in PLL Clock Mode may degrade the quality of the DAC output signal

when compared to an external low jitter clock source.

Figure 34. PLL CLOCK MODE Timing Diagram

The internal PLL has a type four phase-frequency detector (PFD) comparing the CLK2/C reference clock with a

feedback clock to drive a charge pump controlling the VCO operating voltage and maintaining synchronization

between the two clocks. An external low-pass filter is required to control the loop response of the PLL. See the

Low-Pass Filter section for the filter setting calculations. This is the only mode where the LPF filter applies.

The input reference clock N-Divider is selected by CONFIG29 PLL_n(2:0) for values of ÷1, ÷2, ÷4 or ÷8. The

VCO feedback clock M-Divider is selected by CONFIG29 PLL_m(4:0) for values of ÷1, ÷2, ÷4, ÷8, ÷16 or ÷32.

The combination of M-Divider and N-Divider form the clock multiplying ratio of M/N. If the reference clock

frequency is greater than 160MHz, use a N-Divider of ÷2, ÷4 or ÷8 to avoid exceeding the maximum PFD

operating frequency.

For DAC sample rates less than the maximum VCO operating frequency of 910/2 or 455 MHz. The phase noise

of PLL may improved by using the output divider via CONFIG30 VCO_div2. If not using the PLL, clear

CONFIG26 PLL_ena and set CONFIG26 PLL_sleep to reduce power consumption. In some cases, it may be

useful to reset the VCO control voltage by toggling CONFIG30 PLL_LPF_reset.

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