Datasheet

CLK2
CLK2C
CLKVDD (1.8V, Pin 1)
Charge
Pump
N–Divider
(1, 2, 4, 8)
PFD
F
VCOVCO
÷2
F
PLL
M- Divider
( 1,2,4,8,16,32)
PLL Bypass
ClockMultiplyingPLL
External
Loop
Filter
Tointernal
DACclock
distribution
LPF (Pin 64)
F
VCO
/M
F
REF
F
VCO
F
REF
/N
PLL Sleep
PLL_m (4:0)
(CONFIG29)
PLL_n (2:0)
(CONFIG29)
PLL_sleep
(CONFIG26)
VCO_div2
(CONFIG11)
PLL_gain (1:0),
PLL_range(3:0)
(CONFIG30)
PLL_ena
(CONFIG26)
PLL_LPF_reset
(CONFIG30)
F
VCO
/2
IOVDD (3.3V, Pin 9)
CLK1
DA[15:0] A
0
A
1
A
2
A
3
A
N
A
N+1
DB[15:0] B
0
B
1
B
2
B
3
B
N
B
N+1
DAC5688
www.ti.com SLLS880C –DECEMBER 2007–REVISED AUGUST 2010
Figure 35. Functional Block Diagram for PLL
DATA BUS MODES
The DAC5688 supports three DATA BUS MODES:
1. DUAL BUS MODE
2. INTERLEAVED BUS MODE
3. HALF RATE BUS MODE
DUAL BUS MODE
In DUAL BUS MODE, the user inputs data on both DA[15:0] and DB[15:0] ports. This mode is selected by setting
CONFIG1 insel_mode(1:0) = ‘00’. Refer to Figure 36.
Figure 36. DUAL BUS MODE (Dual Clock Mode)
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): DAC5688