Datasheet

CLK 2
1
0.55
2f
-
DAC5688
www.ti.com SLLS880C –DECEMBER 2007–REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)
Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, DVDD, CLKVDD = 1.8V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB, DA[15:0], DB[15:0], SYNC, TXENABLE, CLKO_CLK1, LOCK_CLK1C
CONFIG26 io_1p8_3p3 = 0 (3.3V levels) 2.30
V
IH
High-level input voltage V
CONFIG26 io_1p8_3p3 = 1 (1.8V levels) 1.25
CONFIG26 io_1p8_3p3 = 0 (3.3V levels) 1.00
V
IL
Low-level input voltage V
CONFIG26 io_1p8_3p3 = 1 (1.8V levels) 0.54
I
IH
High-level input current ±20 mA
I
IL
Low-level input current ±20 mA
C
I
CMOS Input capacitance 2 pF
SDO, SDIO I
LOAD
= –100 mA IOVDD
– 0.2
V
OH
V
SDO, SDIO I
LOAD
= –2 mA 0.8 ×
IOVDD
SDO, SDIO I
LOAD
= 100 mA 0.2
V
OL
V
SDO, SDIO I
LOAD
= 2 mA 0.5
Input data rate 0 250 MSPS
t
s(SDENB)
Setup time, SDENB to rising edge of SCLK 20 ns
t
s(SDIO)
Setup time, SDIO valid to rising edge of SCLK 10 ns
t
h(SDIO)
Hold time, SDIO valid to rising edge of SCLK 5 ns
t
SCLK
Period of SCLK 100 ns
t
SCLKH
High time of SCLK 40 ns
t
SCLK
Low time of SCLK 40 ns
t
d(Data)
Data output delay after falling edge of SCLK 10 ns
t
RESET
Minimum RESETB pulse width 25 ns
TIMING PARALLEL DATA INPUT: (DUAL CLOCK and DUAL SYNCHRONOUS CLOCK MODES: Figure 32)
t
s
Setup time 1 ns
CLK1/C = input
t
h
Hold time 1 ns
Max timing offset between CLK1 and CLK2 DUAL SYNCHRONOUS BUS MODE only
t_align ns
rising edges (Typical characteristic)
TIMING PARALLEL DATA INPUT (EXTERNAL CLOCK MODE: Figure 33 and PLL CLOCK MODE: Figure 34)
t
s
Setup time 1 ns
CLKO_CLK1 = input or output. Note: Delay
t
h
Hold time time increases with higher capacitive 1 ns
loads.
t
d(CLKO)
Delay time 4.5 ns
CLOCK INPUT (CLK2/CLK2C)
CLK2/C Duty cycle 40% 60%
CLK2/C Differential voltage
(1)
0.4 1 V
CLK2/C Input common mode 2/3 ×
V
CLKVDD
CLK2C Input Frequency 800 MHz
CLOCK INPUT (CLK1/CLK1C)
CLK1/C Duty cycle 40% 60%
CLK1/C Differential voltage 0.4 1.0 V
CLK1/C Input common mode IOVDD
V
/2
CLK1/C Input Frequency 250 MHz
CLOCK OUTPUT (CLKO)
CLKO Output Frequency
(2)
with 3pF load 160 MHz
(1) Driving the clock input with a differential voltage lower than 1V will result in degraded performance.
(2) Specified by design and simulation. Not production tested. It is recommended to buffer CLKO.
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