Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 16

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FEATURES DESCRIPTION

APPLICATIONS

Resistor

Network

Data

Buffer A

DAC

Data

Buffer D

DAC

DAC A

DAC D

Buffer

Control

Power−Down

Control Logic

OUT

REF

LA0 A1 A2 A3GND

C Block

SCL

SDA

LDAC

REF

IOV

DAC6573

SLAS402 – NOVEMBER 2003

QUAD, 10-Bit, LOW-POWER, VOLTAGE OUTPUT,

C INTERFACE DIGITAL-TO-ANALOG CONVERTER

• Micropower Operation: 500 µA at 3 V V

The DAC6573 is a low-power, quad channel, 10-Bit

• Fast Update Rate: 188 kSPS

buffered voltage output DAC. Its on-chip precision

output amplifier allows rail-to-rail output swing. The

• Power-On Reset to Zero

DAC6573 utilizes an I

C compatible two wire serial

• 2.7-V to 5.5-V Analog Power Supply

interface supporting high-speed interface mode with

• 10-Bit Monotonic

address support of up to sixteen DAC6573s for a total

• I

C™ Interface up to 3.4 Mbps

of 64 channels on the bus.

• Data Transmit Capability

The DAC6573 requires an external reference voltage

• Rail-to-Rail Operation Output Buffer Amplifier

to set the output range of the DAC. The DAC6573

incorporates a power-on-reset circuit that ensures

• Double-Buffered Input Register

that the DAC output powers up at zero volts and

• Address Support for up to Sixteen DAC6573s

remains there until a valid write takes place in the

• Synchronous Update for up to 64 Channels

device. The DAC6573 contains a power-down fea-

• Voltage Translators for all Digital Inputs

ture, accessed via the internal control register, that

reduces the current consumption of the device to 200

• Operation From –40 ° C to 105 ° C

nA at 5 V.

• Small 16 Lead TSSOP Package

The low power consumption of this part in normal

operation makes it ideally suited to portable battery

operated equipment. The power consumption is less

• Process Control

than 3 mW at V

=5 V reducing to 1 µW in

• Data Acquisition Systems

power-down mode.

• Closed-Loop Servo Control

The DAC6573 is available in a 16-lead TSSOP

• PC Peripherals

package.

• Portable Instrumentation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 QUAD, 10-Bit, LOW-POWER, VOLTAGE OUTPUT, I C INTERFACE DIGITAL-TO-ANALOG CONVERTER 2 FEATURES • • • • • • • • • • • • • • DESCRIPTION Micropower Operation: 500 µA at 3 V VDD Fast Update Rate: 188 kSPS Power-On Reset to Zero 2.7-V to 5.5-V Analog Power Supply 10-Bit Monotonic I2C™ Interface up to 3.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) (2) Resolution 10 Bits ±0.5 ±2 LSB ±0.1 ± 0.5 LSB Zero-scale error 5 20 mV Full-scale error -0.15 ±1.0 % of FSR ±1.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified. PARAMETER TEST CONDITIONS TYP MAX UNITS IDD@ VDD=+3.6V to +5.5V VIH= IOVDD and VIL=GND MIN 0.2 1 µA IDD@ VDD =+2.7V to +3.6V VIH= IOVDD and VIL=GND 0.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 TIMING CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS 300 ns 20 + 0.1CB 300 ns High-speed mode, CB = 100 pF max 10 40 ns High-speed mode, CB = 400 pF max 20 80 ns 1000 ns Standard mode tFCL Fall time of SCL signal Fast mode Standard mode tRDA Rise time of SDA signal Fast mode 20 + 0.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 2 2 Channel A 0 −1 0 −1 −2 0.5 0.5 0.25 0.25 DLE − LSB DLE − LSB −2 0 −0.25 0 −0.25 −0.5 −0.5 0 128 256 384 512 640 768 896 1023 Digital Input Code 384 512 640 Digital Input Code Figure 1. Figure 2.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 2 2 Channel D VDD = 2.7 V 0 −1 0 −1 −2 −2 0.5 0.5 DLE − LSB 0.25 0 −0.25 VDD = 2.7 V 1 LE − LSB LE − LSB DLE − LSB Channel C 1 0.25 0 −0.25 −0.5 −0.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SINK CURRENT CAPABILITY AT NEGATIVE RAIL SOURCE CURRENT CAPABILITY AT POSITIVE RAIL 0.150 5.50 Typical For All Channels 0.125 0.100 VOUT − Output Voltage − V VOUT - Output Voltage - V Typical For All Channels VDD = 2.7 V VDD = 5.5 V 0.075 0.050 0.025 5.45 5.40 5.35 DAC Loaded With CFFH VDD = 5.5 V DAC Loaded With 000H 0.000 5.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 2000 TA = 25°C A0 Input (All Other Inputs = GND) VDD = 5 V 1000 1500 Frequency IDD − Supply Current − µA 1200 HISTOGRAM OF CURRENT CONSUMPTION 800 VDD = 5.5 V 600 1000 500 400 VDD = 2.7 V 200 0 0 1 2 3 4 500 520 540 560 580 600 620 640 660 680 700 720 740 5 IDD - Current Consumption - µA VLogic − Logic Input Voltage − V Figure 19.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. ABSOLUTE ERROR† ABSOLUTE ERROR† 24 18 VDD = 5 V, TA = 25°C 16 VDD = 2.7 V, TA = 25°C Channel A Output 14 Output Error − mV Output Error − mV 20 Channel A Output 12 8 Channel B Output Channel B Output Channel B Output 10 6 2 Channel D Output Channel C Output −2 4 Channel D Output 0 0 128 256 384 512 640 Digital Input Code Figure 25.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 THEORY OF OPERATION D/A SECTION The architecture of the DAC6573 consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a generalized block diagram of the DAC architecture. VREFH 50 k 50 k 70 k _ Ref+ Resistor String Ref− DAC Register + VOUT VREFL Figure 27.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 THEORY OF OPERATION (continued) The DAC6573 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 THEORY OF OPERATION (continued) SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 30. Bit Transfer on the I2C Bus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition Figure 31.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 DAC6573 I2C Update Sequence The DAC6573 requires a start condition, a valid I2C address, a control byte, an MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC6573 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the DAC6573. The control byte sets the operational mode of the selected DAC6573.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 Control Byte MSB LSB A3 A2 L1 L0 X Sel1 Sel0 PD0 Table 1. Control Register Bit Descriptions Bit Name Bit Number/Description A3 Extended address bit A2 Extended address bit L1 Load1 (mode select) bit L2 Load0 (mode select) bit Are used for selecting the update mode. 00 Store I2C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the temporary register of a selected channel.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 Table 2. Control Byte C7 C6 C5 C4 C3 C2 C1 C0 MSB7 MSB6 MSB5... A3 A2 Load1 Load0 Don't Care Ch Sel 1 Ch Sel 0 PD0 MSB (PD1) MSB-1 (PD2) MSB-2 ...
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 LDAC Functionality Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four DAC output voltages to be updated simultaneously with temporary register data.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 DAC6573 as a Slave Receiver - High-Speed Mode Figure 34 shows the high-speed mode master transmitter addressing a DAC6573 Slave Receiver with a 7-bit address.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 Master Transmitter Writing to a Slave Receiver (DAC6573) in Standard/Fast Modes All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This control byte specifies the operation mode of DAC6573 and determines which channel of DAC6573 is being accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines whether the following data is power-down data or regular data.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 Master Transmitter Writing to a Slave Receiver (DAC6573) in HS Mode When writing data to the DAC6573 in HS-mode, the master begins to transmit what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 DAC6573 as a Slave Transmitter—Standard and Fast Mode Figure 35 shows the standard and fast mode master receiver addressing a DAC6573 Slave Transmitter with a 7-bit address.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 Master Receiver Reading From a Slave Transmitter (DAC6573) in Standard/Fast Modes When reading data back from the DAC6573, the user begins with an address byte (with R/W = 0) after which the DAC6573 acknowledges by pulling SDA low. This address byte is usually followed by the control byte, which is also acknowledged by the DAC6573. Following this there is a REPEATED START condition by the master and the address is resent with (R/W = 1).
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 Master Receiver Reading From a Slave Transmitter (DAC6573) in HS-Mode When reading data to the DAC6573 in HS-MODE, the master begins to transmit, what is called the HS-Master Code (0000 1XXX) in F/S mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 Table 8. Power-Down Modes of Operation for the DAC6573 CTRL[0] MSB[7] MSB[6] OPERATING MODE 1 0 0 PWD, high impedance DAC output 1 0 1 PWD, 1 kΩ to GND DAC ouptut 1 1 0 PWD, 100 kΩ to GND DAC output 1 1 1 PWD, high impedance DAC output When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 µA at 5 V per channel. However, for the power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V).
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 IOVDD AND VOLTAGE TRANSLATORS IOVDD pin powers the digital input structures of the DAC6573. For single-supply operation, IOVDD can be tied to VDD. For dual-supply operation, the IOVDD pin provides interface flexibility with various CMOS logic families—connect it to the logic supply of the system. Analog circuits and internal logic of the DAC6573 use VDD as the supply voltage. The external logic high inputs get translated to VDD by level shifters.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 APPLICATION INFORMATION The following sections give example circuits and tips for using the DAC6573 in various applications. For more information, contact your local TI representative, or visit the Texas Instruments website at http://www.ti.com. BASIC CONNNECTIONS For many applications, connecting the DAC6573 is extremely simple. A basic connection diagram for the DAC6573 is shown in Figure 38. The 0.
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DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 APPLICATION INFORMATION (continued) DAC6573 IOVDD 1 VOUTA A3 16 2 VOUTB A2 15 3 VREFH A1 14 4 VDD A0 13 5 VREFL Microcontroller or Microprocessor IOVDD 12 6 GND SDA 11 7 VOUTC SCL 10 8 VOUTD LDAC 9 GPIO-1 GPIO-2 NOTE: DAC6573 power and input/output connections are omitted for clarity, except I C Inputs. Figure 39.
PAGE 28
DAC6573 www.ti.com SLAS402 – NOVEMBER 2003 APPLICATION INFORMATION (continued) VDD = 5 V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total typical current required (with a 5-kΩ load on a single DAC output) is: 600 µA + (5 V / 5 kΩ) = 1.6 mA The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 400 µV for 1.6 mA of current drawn from it. This corresponds to a 0.08 LSB error for a 0 V to 5 V output range. 15 V REF02 5V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC6573IPWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC6573IPWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.