Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VSSOP 10

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FEATURES DESCRIPTION

APPLICATIONS

Resistor

Network

Data

Buffer A

DAC

Data

Buffer D

DAC

DAC A

DAC D

Buffer

Control

Power-Down

Control Logic

OUT

A0 A1 GND

Block

SCL

SDA

DAC6574

SLAS408 – DECEMBER 2003

QUAD, 10-BIT, LOW-POWER, VOLTAGE OUTPUT,

C INTERFACE DIGITAL-TO-ANALOG CONVERTER

• Micropower Operation: 500 µA at 3 V V

The DAC6574 is a low-power, quad channel, 10-bit

• Fast Update Rate: 188 kSPS

buffered voltage output DAC. Its on-chip precision

output amplifier allows rail-to-rail output swing to be

• Per-channel Power-down Capability

achieved. The DAC6574 utilizes an I

C compatible

• Power-On Reset to Zero

two wire serial interface supporting high-speed

• 2.7-V to 5.5-V Analog Power Supply

interface mode with address support of up to four

• 10-Bit Monotonic

DAC6574s for a total of 16 channels on the bus.

• I

C™ Interface Up to 3.4 Mbps

The DAC6574 uses V

and GND to set the output

• Data Transmit Capability

range of the DAC. The DAC6574 incorporates a

power-on-reset circuit that ensures that the DAC

• On-Chip Output Buffer Amplifier, Rail-to-Rail

output powers up at zero volts and remains there until

Operation

a valid write takes place to the device. The DAC6574

• Double-Buffered Input Register

contains a per-channel power-down feature, ac-

• Address Support for up to Four DAC6574s

cessed via the internal control register, that reduces

• Synchronous Update Support for up to 16

the current consumption of the device to 200 nA at 5

Channels

• Operation From –40 ° C to 105 ° C

The low power consumption of this part in normal

• Small 10 Lead MSOP Package

operation makes it ideally suited to portable battery

operated equipment. The power consumption is less

than 3mW at V

= 5 V reducing to 1 µW in

power-down mode.

• Process Control

• Data Acquisition Systems

TI offers a variety of data converters with I

interface. See DACx57x family of 16/12/10/8 bit,

• Closed-Loop Servo Control

single and quad channel DACs. Also see ADS7823

• PC Peripherals

and ADS1100, 12-bit octal channel and 16-bit single

• Portable Instrumentation

channel ADCs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 QUAD, 10-BIT, LOW-POWER, VOLTAGE OUTPUT, I C INTERFACE DIGITAL-TO-ANALOG CONVERTER 2 FEATURES • • • • • • • • • • • • • • DESCRIPTION Micropower Operation: 500 µA at 3 V VDD Fast Update Rate: 188 kSPS Per-channel Power-down Capability Power-On Reset to Zero 2.7-V to 5.5-V Analog Power Supply 10-Bit Monotonic I2C™ Interface Up to 3.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 10 Bits ±0.5 ±2 LSB ±0.1 ±0.5 LSB Zero-scale error 5 20 mV Full-scale error -0.15 ±1.0 % of FSR ±1.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 TIMING CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP Standard mode tFDA Fast mode Fall time of SDA signal CB Capacitive load for SDA and SCL tSP Pulse width of spike suppressed ns 10 80 ns 20 160 ns Standard mode 4.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Channel C 2 VDD = 5 V Channel D LE − LSB 1 0 −1 −2 0.25 0.25 −0.25 −0.5 128 256 384 512 640 Digital Input Code 768 896 1023 0 768 896 1023 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 2 VDD = 2.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. ZERO-SCALE ERROR vs TEMPERATURE ZERO-SCALE ERROR vs TEMPERATURE 20 15 VDD = 2.7 V 15 Zero-Scale Error − mV Zero-Scale Error − mV VDD = 5 V CH A CH C CH D 10 CH B 5 10 CH A CH C CH D 5 CH B 0 −40 −10 20 50 80 −40 −10 TA − Free−Air Temperature − °C Figure 10. FULL-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 80 20 VDD = 5 V VDD = 2.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SOURCE CURRENT CAPABILITY AT POSITIVE RAIL SUPPLY CURRENT vs DIGITAL INPUT CODE 2.7 800 700 IDD − Supply Current − µA VOUT − Output Voltage − V Typical For All Channels 2.6 2.5 2.4 DAC Loaded With CFFH VDD = 2.7 V VDD = 5.5 V 600 500 400 VDD = 2.7 V 300 200 100 2.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. HISTOGRAM OF CURRENT CONSUMPTION EXITING POWER-DOWN MODE 2000 6 VDD = 2.7 V VOUT − Output Voltage − V 1500 Frequency 5 1000 500 0 VDD = 5 V Powerup to Code 1000 4 3 2 1 0 −1 400 420 440 460 480 500 520 540 560 580 600 620 Time (2 µs/div) IDD − Current Consumption − µA Figure 21. Figure 22. LARGE SIGNAL SETTLING TIME LARGE SIGNAL SETTLING TIME 3.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 THEORY OF OPERATION D/A SECTION The architecture of the DAC6574 consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a generalized block diagram of the DAC architecture. VDD 50 k 50 k 70 k _ Ref+ Resistor String Ref- DAC Register + VOUT GND Figure 27.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 THEORY OF OPERATION (continued) The DAC6574 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 THEORY OF OPERATION (continued) SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 30. Bit Transfer on the I2C Bus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition Figure 31.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 2 DAC6574 I C Update Sequence The DAC6574 requires a start condition, a valid I2C address, a control byte, an MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC6574 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the DAC6574. The control byte sets the operational mode of the selected DAC6574.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 Control Byte MSB LSB 0 0 L1 L0 X Sel1 Sel0 PD0 Table 1. Control Register Bit Descriptions Bit Name Bit Number/Description L1 Load1 (Mode Select) Bit L2 Load0 (Mode Select) Bit 14 00 Store I2C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the temporary register of a selected channel. This mode does not change the DAC output of the selected channel. 01 Update selected DAC with I2C data.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 Table 2. Control Byte C7 C6 C5 C4 C3 C2 C1 C0 MSB7 MSB6 MSB5... 0 0 Load1 Load0 Don't Care Ch Sel 1 Ch Sel 0 PD0 MSB (PD1) MSB-1 (PD2) MSB-2 ...
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 DAC6574 Registers Table 3. DAC6574 Architecture Register Descriptions REGISTER DESCRIPTION CTRL[7:0] Stores 8-Bit wide control byte sent by the master MSB[7:0] Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit power-down data. LSB[7:0] Stores the 2 least significant bits of unsigned binary data sent by the master (in LSB[7] and LSB[6]).
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 DAC6574 as a Slave Receiver - High-Speed Mode Figure 34 shows the high-speed mode master transmitter addressing a DAC6574 Slave Receiver with a 7-bit address.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 Master Transmitter Writing to a Slave Receiver (DAC6574) in Standard/Fast Modes All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This control byte specifies the operation mode of DAC6574 and determines which channel of DAC6574 is being accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the following data is power-down data or regular data.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 Master Transmitter Writing to a Slave Receiver (DAC6574) in HS Mode When writing data to the DAC6574 in HS-mode, the master begins to transmit what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 DAC6574 as a Slave Transmitter—Standard and Fast Mode Figure 35 shows the standard and fast mode master transmitter addressing a DAC6574 Slave Transmitter with a 7-bit address.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 Master Receiver Reading From a Slave Transmitter (DAC6574) in Standard/Fast Modes When reading data back from the DAC6574, the user begins with an address byte (with R/W = 0) after which the DAC6574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which is also acknowledged by the DAC6574. Following this there is a REPEATED START condition by the Master and the address is resent with (R/W = 1).
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 Master Receiver Reading From a Slave Transmitter (DAC6574) in HS-Mode When reading data to the DAC6574 in HS-MODE, the master begins to transmit, what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge.
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DAC6574 www.ti.com SLAS408 – DECEMBER 2003 Table 8. Power-Down Modes of Operation for the DAC6574 CTRL[0] MSB[7] MSB[6] OPERATING MODE 1 0 0 High Impedance Output 1 0 1 1 kΩ to GND 1 1 0 100 kΩ to GND 1 1 1 High Impedance When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 µA at 5 V per channel. However, for the power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V).
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DAC6574 SLAS408 – DECEMBER 2003 www.ti.com CROSSTALK The DAC6574 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel is typically less than 0.01 LSBs. The ac crosstalk measured (for a full-scale, 1 kHz sine wave output generated at one channel, and measured at the remaining output channel) is typically under -100 dB.
PAGE 25
DAC6574 www.ti.com SLAS408 – DECEMBER 2003 APPLICATION INFORMATION The following sections give example circuits and tips for using the DAC6574 in various applications. For more information, contact your local TI representative, or visit the Texas Instruments website at http://www.ti.com. BASIC CONNNECTIONS For many applications, connecting the DAC6574 is extremely simple. A basic connection diagram for the DAC6574 is shown in Figure 38. The 0.
PAGE 26
DAC6574 www.ti.com SLAS408 – DECEMBER 2003 APPLICATION INFORMATION (continued) DAC6574 VDD 1 VOUTA A1 10 2 VOUTB A0 9 3 GND VDD 8 4 VOUTC SDA 7 5 VOUTD SCL 6 Microcontroller or Microprocessor GPIO-1 GPIO-2 NOTE: DAC6574 power and input/output connections are omitted for clarity, except I C Inputs. Figure 39.
PAGE 27
DAC6574 www.ti.com SLAS408 – DECEMBER 2003 APPLICATION INFORMATION (continued) external reference to the device. Due to low power consumption of DAC6574, load regulation errors are negligible. In order to avoid excess power consumption at the Schmitt-triggered inputs of DAC6574, the precision reference voltage should be close to the I2C bus pullup voltage. For 3-V, 3.3-V and 5-V I2C bus pullup voltages, REF2930, REF2933 and REF02 precision voltage references are recommended respectively.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC6574IDGSR Package Package Pins Type Drawing VSSOP DGS 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC6574IDGSR VSSOP DGS 10 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.