Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOIC 16

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FEATURES:

● SERIAL DIGITAL INTERFACE

● VOLTAGE OUTPUT: ±10V, ±5V, 0 to +10V

● ±1 LSB INTEGRAL LINEARITY

●

16-BIT MONOTONIC OVER TEMPERATURE

● PRECISION INTERNAL REFERENCE

● LOW NOISE: 120nV/√Hz Including Reference

● 16-LEAD PLASTIC AND CERAMIC SKINNY

DIP AND PLASTIC SO PACKAGES

16-Bit DIGITAL-TO-ANALOG CONVERTER

With Serial Data Interface

DESCRIPTION

The DAC714 is a complete monolithic digital-to-

analog (D/A) converter including a +10V temperature com-

pensated reference, current-to-voltage amplifier, a high-speed

synchronous serial interface, a serial output which allows

cascading multiple converters, and an asynchronous clear

function which immediately sets the output voltage to midscale.

The output voltage range is ±10V, ±5V, or 0 to +10V while

operating from ±12V or ±15V supplies. The gain and bipolar

offset adjustments are designed so that they can be set via

external potentiometers or external D/A converters. The

output amplifier is protected against short circuit to ground.

The 16-pin DAC714 is available in a plastic 0.3" DIP, ceramic

0.3" CERDIP, and wide-body plastic SO package. The

DAC714P, U, HB, and HC are specified over the –40°C to

+85°C temperature range while the DAC714HL is specified

over the 0°C to +70°C range.

OUT

REF OUT

+10V

Reference

Circuit

16-Bit D/A Converter

D/A Latch

SDO

FB2

Input Shift Register

SDI

CLK

CLR

Offset AdjustGain

Adjust

BPO

DAC714

SBAS032A – JULY 1997 – REVISED NOVEMBER 2005

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (22 pages)

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DAC714 DA C71 4 DAC 714 SBAS032A – JULY 1997 – REVISED NOVEMBER 2005 16-Bit DIGITAL-TO-ANALOG CONVERTER With Serial Data Interface FEATURES: DESCRIPTION ● SERIAL DIGITAL INTERFACE The DAC714 is a complete monolithic digital-toanalog (D/A) converter including a +10V temperature compensated reference, current-to-voltage amplifier, a high-speed synchronous serial interface, a serial output which allows cascading multiple converters, and an asynchronous clear function which immediately sets the output vo
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ABSOLUTE MAXIMUM RATINGS(1) +VCC to Common .................................................................... 0V to +17V –VCC to Common .................................................................... 0V to –17V +VCC to –VCC ....................................................................................... 34V ACOM to DCOM ............................................................................... ±0.5V Digital Inputs to Common ............................................. –1V to (VCC –0.
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ELECTRICAL CHARACTERISTICS At TA = +25°C, +VCC = +12V and +15V, –VCC = –12V, and –15V, unless otherwise noted.
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TIMING SPECIFICATIONS TRUTH TABLE TA = –40°C to +85°C, +VCC = +12V or +15V, –VCC = –12V or –15V.
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TYPICAL CHARACTERISTICS POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY LOGIC vs V LEVEL 1k 2.0 –VCC 100 I Digital Input (µA) [Change in FSR] / [Change in Supply Voltage] (ppm of FSR/ %) At TA = +25°C, VCC = ±15V, unless otherwise noted. +VCC 10 1 100 1k 10k 100k A0, A1 CLR 0 SDI –1.0 –2.0 –0.85 0.1 10 1.0 1M 0 0.85 1.7 2.55 3.4 4.25 5.1 5.95 6.
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DISCUSSION OF SPECIFICATIONS LINEARITY ERROR Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points of the transfer characteristic. DIFFERENTIAL LINEARITY ERROR Differential linearity error (DLE) is the deviation from 1LSB of an output change from one adjacent state to the next.
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Gain Adjust VREF OUT +VCC – VCC 14 12 7 15 180Ω 15kΩ +10V Reference 10 RFB2 11 RBPO 13 Offset Adjust 9 VOUT 250Ω 10kΩ +2.5V 9750Ω 10kΩ –VCC D/A Switches CLK 1 A1 3 CLR 16 A0 2 SDI 4 SDO 5 DAC Latch 16 Shift Register 8 6 ACOM DCOM FIGURE 1. DAC714 Block Diagram. +VCC ESD Protection Circuit Range of Gain Adjust ≈ ±0.3% + Full Scale 6.8V Analog Output 1kΩ Digital Input 5pF –VCC FIGURE 2. Equivalent Circuit of Digital Inputs.
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DAC714 CALIBRATION VALUES DIGITAL INPUT CODE ANALOG OUTPUT (V) BINARY TWO’S BIPOLAR UNIPOLAR COMPLEMENT, BTC 20V RANGE 10V RANGE DESCRIPTION 7FFFH | 4000H | 0001H +9.999695 +9.999847 + Full Scale –1LSB +5.000000 +7.500000 3/4 Scale +0.000305 +5.000153 BPZ + 1LSB 0000H 0.000000 +5.000000 Bipolar Zero (BPZ) FFFFH | C000H | 8000H –0.000305 +4.999847 BPZ – 1LSB –5.000000 +2.500000 1/4 Scale –10.00000 0.
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GAIN AND OFFSET ADJUST Connections Using Potentiometers GAIN and OFFSET adjust pins provide for trim using external potentiometers. 15-turn potentiometers provide sufficient resolution. Range of adjustment of these trims is at least ±0.3% of Full Scale Range. Refer to Figure 6. Using D/A Converters The GAIN ADJUST and OFFSET ADJUST circuits of the DAC714 have been arranged so that these points may be easily driven by external D/A converters. Refer to Figure 7.
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Internal +10V Reference VREF OUT 12 P1 1kΩ 180Ω R1 100Ω Gain Adjust 14 Offset Adjust R2 2MΩ 10kΩ to 100kΩ 13 15kΩ 10kΩ 9.75kΩ RFB2 9 IDAC 0-2mA –VCC R3 27kΩ 10 10kΩ 8 +VCC VOUT For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R3 are standard ±1% values. Range of adjustment at least ±0.3% FSR. ACOM FIGURE 6a. Manual Offset and Gain Adjust Circuits; Unipolar Mode (0V to +10V output range).
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Internal +10V Reference VREF OUT 12 Bipolar Offset 180Ω R2 1.3kΩ R1 200Ω 250Ω 10kΩ +10V 11 10kΩ Gain Adjust –10V 14 Offset Adjust 5kΩ 13 15kΩ 9.75kΩ 10kΩ RFB2 10 Suggested Op Amps OPA177GP, GS or OPA604AP, AU R4 24.3kΩ R3 11.8kΩ 10kΩ RFB VREF A 0 to +10V IDAC 0-2mA Suggested Op Amps OPA177GP, GS: Single or OPA2604AP, AU: Dual 9 ±10V VOUT 0 to +10V RFB VREF B DAC714 For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R4 tolerance: ±1%.
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4 Data 2 Data Latch 3 Update 1 CLK +5V 16 4 2 3 1 +5V 16 4 2 3 1 +5V 16 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 To other DACs FIGURE 8a. Cascaded Serial Bus Connection with Synchronous Update. DAC3 DAC2 DAC1 Clock(1) Data F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 Data Latch Update FIGURE 8b. Timing Diagram For Figure 8a. 12 DAC714 www.ti.
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4 Data 2 Data Latch 3 Update 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 +5V 4 2 3 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 +5V 4 2 3 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 To other DACs +5V FIGURE 9a. Cascaded Serial Bus Connection with Asynchronous Update. DAC3 DAC2 DAC1 Data Latch(1) Data F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 Update FIGURE 9b. Timing Diagram For Figure 9a. DAC714 SBAS032A www.ti.
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Data Data Latch 1 Update 4 2 3 1 CLK 16 CLR 4 Data Latch 2 2 3 1 16 4 Data Latch 3 2 3 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 FIGURE 10a. Parallel Bus Connection. DAC1 DAC2 DAC3 Clock(1) Data F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 Data Latch 1 Data Latch 2 Data Latch 3 Update FIGURE 10b. Timing Diagram For Figure 10a. 14 DAC714 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC714U/1K Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC714U/1K SOIC DW 16 1000 367.0 367.0 38.
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