Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOT 23 6

APPLICATIONS

● PORTABLE BATTERY-POWERED

INSTRUMENTS

● DIGITAL GAIN AND OFFSET

ADJUSTMENT

● PROGRAMMABLE VOLTAGE AND

CURRENT SOURCES

Low-Power, Rail-to-Rail Output, 12-Bit Serial Input

DIGITAL-TO-ANALOG CONVERTER

DESCRIPTION

The DAC7512 is a low-power, single, 12-bit buffered voltage

output Digital-to-Analog Converter (DAC). Its on-chip preci-

sion output amplifier allows rail-to-rail output swing to be

achieved. The DAC7512 uses a versatile three-wire serial

interface that operates at clock rates up to 30MHz and is

compatible with standard SPI

™

, QSPI

™

, Microwire

™

, and

DSP interfaces.

The reference for the DAC7512 is derived from the power

supply, resulting in the widest dynamic output range possible.

The DAC7512 incorporates a power-on reset circuit that

ensures that the DAC output powers up at 0V and remains

there until a valid write takes place in the device. The

DAC7512 contains a power-down feature, accessed over the

serial interface, that can reduce the current consumption of

the device to 50nA at 5V.

The low power consumption of this part in normal operation

makes it ideally suited to portable battery-operated equip-

ment. The power consumption is 0.7mW at 5V reducing to

1µW in power-down mode.

The DAC7512 is available in a SOT23-6 package and an

MSOP-8 package.

DAC7512

FEATURES

● microPOWER OPERATION:

135µA at 5V

● POWER-DOWN: 200nA at 5V, 50nA at 3V

● POWER SUPPLY: +2.7V to +5.5V

●

TESTED MONOTONIC BY DESIGN

● POWER-ON RESET TO 0V

● THREE POWER-DOWN FUNCTIONS

● LOW POWER SERIAL INTERFACE WITH

SCHMITT-TRIGGERED INPUTS

● ON-CHIP OUTPUT BUFFER AMPLIFIER,

RAIL-TO-RAIL OPERATION

● SYNC INTERRUPT FACILITY

● SOT23-6 AND MSOP-8 PACKAGES

Power-On

Reset

DAC

REF (+) REF (–)

12-Bit

DAC

Output

Buffer

Input

Control

Logic

Power-Down

Control Logic

Resistor

Network

SYNC

SCLK D

GND

OUT

SPI and QSPI are registered trademarks of Motorola.

Microwire is a registered trademark of National Semiconductor.

DAC7512

SBAS156B – JULY 2002

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (25 pages)

PAGE 1
DAC7512 DAC 751 2 DAC 7512 SBAS156B – JULY 2002 Low-Power, Rail-to-Rail Output, 12-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● microPOWER OPERATION: 135µA at 5V ● POWER-DOWN: 200nA at 5V, 50nA at 3V ● POWER SUPPLY: +2.7V to +5.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VDD to GND ........................................................................... –0.3V to +6V Digital Input Voltage to GND .................................. –0.3V to +VDD + 0.3V VOUT to GND ........................................................... –0.3V to +VDD + 0.3V Operating Temperature Range ..................................... –40°C to +105°C Storage Temperature Range .........................................
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ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V; RL = 2ký to GND; CL = 200pF to GND.
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TIMING CHARACTERISTICS(1, 2) VDD = +2.7V to +5.5V; all specifications –40°C to +105°C, unless otherwise noted. DAC7512E, N PARAMETER t1(3) t2 t3 t4 t5 t6 t7 t8 DESCRIPTION CONDITIONS MIN TYP MAX UNITS VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 50 33 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 13 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 22.5 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 0 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 5 5 ns ns VDD = 2.7V to 3.6V VDD = 3.
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TYPICAL CHARACTERISTICS: VDD = +5V At TA = +25°C, +VDD = +5V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) LE (LSB) 16.0 12.0 8.0 4.0 0.0 –4.0 –8.0 –12.0 –16.0 16.0 12.0 8.0 4.0 0.0 –4.0 –8.0 –12.0 –16.0 1.0 1.0 0.5 0.5 DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 0.0 –0.5 –1.0 0.0 –0.5 –1.
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TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = +25°C, +VDD = +5V, unless otherwise noted.
PAGE 7
TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = +25°C, +VDD = +5V, unless otherwise noted.
PAGE 8
TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = +25°C, +VDD = +5V, unless otherwise noted. EXITING POWER-DOWN (800H Loaded) CODE CHANGE GLITCH Loaded with 2kΩ and 200pF to GND. Code Change: 800H to 7FFH. VOUT (20mV/div) CLK (5V/div) VOUT (1V/div) Time (5µs/div) Time (0.5µs/div) TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, +VDD = +2.7V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) LE (LSB) 16.0 12.0 8.0 4.0 0.0 –4.0 –8.0 –12.0 –16.0 16.0 12.
PAGE 9
TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = +25°C, +VDD = +2.7V, unless otherwise noted. FULL-SCALE ERROR vs TEMPERATURE 30 20 20 10 10 Error (mV) Error (mV) ZERO-SCALE ERROR vs TEMPERATURE 30 0 0 –10 –10 –20 –20 –30 –40 0 40 80 –30 –40 120 0 Temperature (°C) IDD HISTOGRAM 3000 40 80 120 Temperature (°C) SOURCE AND SINK CURRENT CAPABILITY 3 VDD = +3V VREF tied to VDD.
PAGE 10
TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = +25°C, +VDD = +2.7V, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL-SCALE SETTLING TIME 2500 CLK (2.7V/div) IDD (µA) 2000 1500 1000 Full-Scale Code Change 000H to FFFH Output Loaded with 2kΩ and 200pF to GND 500 VOUT (1V/div) 0 0 1 2 3 4 5 Time (1µs/div) VLOGIC (V) HALF-SCALE SETTLING TIME FULL-SCALE SETTLING TIME CLK (2.7V/div) CLK (2.
PAGE 11
TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = +25°C, +VDD = +2.7V, unless otherwise noted. EXITING POWER-DOWN (800H Loaded) CODE CHANGE GLITCH Loaded with 2kΩ and 200pF to GND. Code Change: 800H to 7FFH. VOUT (20mV/div) CLK (2.7V/div) VOUT (1V/div) Time (0.5µs/div) Time (5µs/div) THEORY OF OPERATION DAC SECTION R The DAC7512 is fabricated using a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier.
PAGE 12
SERIAL INTERFACE The DAC7512 has a three-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, and Microwire interface standards as well as most Digital Signal Processors (DSPs). See the Serial Write Operation timing diagram for an example of a typical write sequence. The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of SCLK.
PAGE 13
MicrowireTM Amplifier Resistor String DAC VOUT DAC7513(1) CS SYNC SK SCLK SO DIN NOTE: (1) Additional pins omitted for clarity. Power-down Circuitry Resistor Network Microwire is a registered trademark of National Semiconductor. FIGURE 7. DAC7512 to Microwire Interface. DAC7512 TO 68HC11 INTERFACE FIGURE 5. Output Stage During Power-Down. All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down.
PAGE 14
This is an output voltage range of ±5V with 000H corresponding to a –5V output and FFFH corresponding to a +5V output. +15 +5V LAYOUT REF02 A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. 135µA As the DAC7512 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors.
PAGE 15
PACKAGE DRAWINGS MPDS028B – JUNE 1997 – REVISED SEPTEMBER 2001 DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,08 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/C 08/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 DAC7512 SBAS156B www.ti.
PAGE 16
PACKAGE DRAWINGS (Cont.) MPDS026D DBV (R-PDSO-G6) FEBRUARY 1997 REVISED FEBRUARY 2002 PLASTIC SMALL-OUTLINE 0,95 6X 6 0,50 0,25 0,20 M 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0° 8 ° 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-5/G 01/02 NOTES: A. B. C. D. 16 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC7512E/250 Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.4 1.4 8.0 12.0 Q1 VSSOP DGK 8 250 180.0 12.4 DAC7512E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC7512N/250 SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7512E/250 VSSOP DGK 8 250 210.0 185.0 35.0 DAC7512E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 DAC7512N/250 SOT-23 DBV 6 250 180.0 180.0 18.0 DAC7512N/3K SOT-23 DBV 6 3000 180.0 180.0 18.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.