Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) QFN 16

3 mm x 3 mm

Actual Size

Interface

Logic

Input

DAC

String

DAC A

Power-Down

Logic

Power-On

Reset

IOV

REFA

FBA

OUT

REFB

GND

CLR

DCEN

SDIN

SYNC

SCLK

Input

DAC

String

DAC B

FBB

OUT

SDO

FUNCTIONAL BLOCK DIAGRAM

DAC7552

www.ti.com

SLAS442D –JANUARY 2005– REVISED JUNE 2011

12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

Check for Samples: DAC7552

FEATURES

DESCRIPTION

The DAC7552 is a 12-bit, dual-channel,

• 2.7-V to 5.5-V Single Supply

voltage-output DAC with exceptional linearity and

• 12-Bit Linearity and Monotonicity

monotonicity. Its proprietary architecture minimizes

• Rail-to-Rail Voltage Output

undesired transients such as code-to-code glitch and

• Settling Time: 5 µs (Max)

channel-to-channel crosstalk. The low-power

DAC7552 operates from a single 2.7-V to 5.5-V

• Ultralow Glitch Energy: 0.1 nVs

supply. The DAC7552 output amplifiers can drive a

• Ultralow Crosstalk: –100 dB

2-kΩ, 200-pF load rail-to-rail with 5-µs settling time;

• Low Power: 440 µA (Max)

the output range is set using an external voltage

• Per-Channel Power Down: 2 µA (Max)

reference.

• Power-On Reset to Zero Scale

The 3-wire serial interface operates at clock rates up

• SPI-Compatible Serial Interface: Up to 50 MHz

to 50 MHz and is compatible with SPI, QSPI,

• Daisy-Chain Capability

Microwire™, and DSP interface standards. The

outputs of all DACs may be updated simultaneously

• Asynchronous Hardware Clear

or sequentially. The parts incorporate a

• Simultaneous or Sequential Update

power-on-reset circuit to ensure that the DAC outputs

• Specified Temperature Range: –40°C to 105°C

power up to zero volts and remain there until a valid

• Small 3-mm × 3-mm, 16-Lead QFN Package

write cycle to the device takes place. The parts

contain a power-down feature that reduces the

APPLICATIONS

current consumption of the device to under 2 µA.

• Portable Battery-Powered Instruments

The small size and low-power operation makes the

• Digital Gain and Offset Adjustment

DAC7552 ideally suited for battery-operated portable

applications. The power consumption is typically

• Programmable Voltage and Current Sources

1.5 mW at 5 V, 0.75 mW at 3 V, and reduces to 1 µW

• Programmable Attenuators

in power-down mode.

• Industrial Process Control

The DAC7552 is available in a 16-lead QFN package

and is specified over –40°C to 105°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

PAGE 1
Actual Size 3 mm x 3 mm DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC7552 FEATURES DESCRIPTION • • • • • • • • • • • • • • • The DAC7552 is a 12-bit, dual-channel, voltage-output DAC with exceptional linearity and monotonicity. Its proprietary architecture minimizes undesired transients such as code-to-code glitch and channel-to-channel crosstalk.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time 0 RL = 2 kΩ; 0 pF < CL < 200 pF Slew rate VREF V 5 µs 1.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 TIMING CHARACTERISTICS (1) www.ti.com (2) VDD = 2.7 V to 5.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com PIN DESCRIPTION VFBA VREFA CLR SDIN RGT PACKAGE (TOP VIEW) 1 16 15 14 13 12 2 11 3 10 4 9 6 7 8 SCLK SYNC IOVDD SDO DCEN 5 VFBB VREFB PD VOUTA VDD GND VOUTB Terminal Functions TERMINAL NO. (1) DESCRIPTION NAME 1 VOUTA Analog output voltage from DAC A 2 VDD Analog voltage supply input 3 GND (1) Ground 4 VOUTB Analog output voltage from DAC B 5 VFBB DAC B amplifier sense input.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 Channel A VREF = 4.096 V Linearity Error − LSB Linearity Error − LSB 1 VDD = 5 V 0.5 0 −0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 4096 −0.5 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 Figure 2. Figure 3.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE 3 3 VDD = 2.7 V, VREF = 2.5 V 2 2 Zero-Scale Error − mV Zero-Scale Error − mV VDD = 5 V, VREF = 4.096 V Channel A 1 Channel B 1 Channel A 0 0 Channel B −1 −40 −10 20 50 −1 −40 80 TA − Free-Air Temperature − °C 20 50 80 TA − Free-Air Temperature − °C Figure 6. Figure 7.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 0.2 5.50 Typical for All Channels VDD = 2.7 V, VREF = 2.5 V 0.15 VO − Output Voltage − V VO − Output Voltage − V Typical for All Channels 0.1 VDD = 5.5 V, VREF = 4.096 V VDD = VREF = 5.5 V 5.40 5.30 0.05 DAC Loaded with 000h 0 0 5 10 ISINK − Sink Current − mA DAC Loaded with FFFh 5.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 400 400 I DD − Supply Current − µ A I DD − Supply Current − µ A All DACs Powered, No Load, VREF = 2.5 V 350 VDD = 5.5 V, VREF = 4.096 V 300 VDD = 2.7 V, VREF = 2.5 V 250 350 300 250 All Channels Powered, No Load 200 −40 −10 20 50 80 TA − Free-Air Temperature − °C 200 2.7 110 3.8 4.1 4.5 4.8 5.2 5.5 Figure 15.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V TOTAL ERROR - 5 V 4 1500 VDD = 5 V, VREF = 4.096 V, TA = 255C VDD = 2.7 V, VREF = 2.5 V Total Error − mV f − Frequency − Hz 2 1000 Channel A Output 0 Channel B Output 500 −2 0 −4 0 239 249 259 269 279 289 299 309 319 IDD − Current Consumption − mA Figure 18. 512 1024 1536 2048 2560 3072 3584 4095 Digital Input Code Figure 19. TOTAL ERROR - 2.
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DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) LARGE-SIGNAL SETTLING TIME - 5 V LARGE-SIGNAL SETTLING TIME - 2.7 V 5 3 VDD = 2.7 V, VREF = 2.5 V Output Loaded With 200 pF to GND Code 41 to 4055 VDD = 5 V, VREF = 4.096 V Output Loaded With 200 pF to GND Code 41 to 4055 VO − Output Voltage − V VO − Output Voltage − V 4 3 2 2 1 1 0 0 t − Time − 5 s/div t − Time − 5 s/div Figure 23.
PAGE 12
DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) CHANNEL-TO-CHANNEL CROSSTALK FOR A FULL-SCALE SWING VO - VO - (5 mV/Div) (5 mV/Div) DIGITAL FEEDTHROUGH ERROR Trigger Pulse Trigger Pulse Time - (400 nS/Div) Time - (400 nS/Div) Figure 26. Figure 27. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY THD − Total Harmonic Distortion − dB −40 VDD = 5 V, VREF = 4.
PAGE 13
DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 3-Wire Serial Interface The DAC7552 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface. Table 1. Serial Interface Programming CONTROL DATA BITS DAC(s) FUNCTION DB15 DB14 DB13 DB12 DB11-DB10 0 0 0 0 data A Single Channel Store. The input register of channel A is updated. 0 0 1 0 data B Single Channel Store. The input register of channel B is updated.
PAGE 14
DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com THEORY OF OPERATION D/A SECTION DAC External Reference Input The architecture of the DAC7552 consists of a string DAC followed by an output buffer amplifier. Figure 29 shows a generalized block diagram of the DAC architecture. Two separate reference pins are provided for two DACs, providing maximum flexibility. VREFA serves DAC A and VREFB serves DAC B. VREFA and VREFB can be externally shorted together for simplicity.
PAGE 15
DAC7552 www.ti.com Asynchronous Clear The DAC7552 output is asynchronously set to zero-scale voltage immediately after the CLR pin is brought low. The CLR signal resets all internal registers and therefore behaves like the Power-On Reset. The DAC7552 updates at the first rising edge of the SYNC signal that occurs after the CLR pin is brought back to high. IOVDD and Level Shifters The DAC7552 can be used with different logic families that require a wide range of supply voltages (from 1.8 V to 5.5 V).
PAGE 16
DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 INTEGRAL AND DIFFERENTIAL LINEARITY The DAC7552 uses precision thin-film resistors providing exceptional linearity and monotonicity. Integral linearity error is typically within (+/-) 0.35 LSBs, and differential linearity error is typically within (+/-) 0.08 LSBs. www.ti.
PAGE 17
DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation. Once R2 and R1 set the gain to include some minimal over-range, a DAC7552 channel could be used to set the required offset voltage. Residual errors are not an issue for loop accuracy because offset and gain errors could be tolerated.
PAGE 18
DAC7552 SLAS442D – JANUARY 2005 – REVISED JUNE 2011 www.ti.com REVISION HISTORY Changes from Revision C (December 2005) to Revision D Page • Changed to Revision D, June 2011 ...................................................................................................................................... 1 • Changed row 4, DAC(s) column from A to A-B, row 5, from A to B and row 6, from B to A-B ..........................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7552IRGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC7552IRGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7552IRGTR QFN RGT 16 3000 338.1 338.1 20.6 DAC7552IRGTT QFN RGT 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.