Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 16

DAC7565

24-BitShiftRegister

SYNC

SCLK

DataBufferA

DACRegisterA

DataBufferB

DACRegisterB

DataBufferC

DACRegisterC

DataBufferD

DACRegisterD

Buffer

Control

ControlLogic

2.5V

Reference

Power-Down

ControlLogic

12-BitDAC

V A

OUT

V B

OUT

V C

OUT

V D

OUT

GND

LDAC ENABLE

RSTSEL

RST

DAC7565

REF REF

H/V OUT

IOV

REF

DAC7565

www.ti.com

SBAS412B –FEBRUARY 2008–REVISED MARCH 2011

12-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output

Digital-to-Analog Converter with 2.5V, 2ppm/°C Internal Reference

Check for Samples: DAC7565

FEATURES

DESCRIPTION

The DAC7565 is a low-power, voltage-output,

234

• Relative Accuracy: 0.5LSB

four-channel, 12-bit digital-to-analog converter (DAC).

• Glitch Energy: 0.15nV-s

The device includes a 2.5V, 2ppm/°C internal

• Internal Reference:

reference (enabled by default), giving a full-scale

output voltage range of 2.5V. The internal reference

– 2.5V Reference Voltage (enabled by default)

has an initial accuracy of 0.02% and can source up to

– 0.004% Initial Accuracy (typ)

20mA at the V

REF

H/V

REF

OUT pin. The device is

– 2ppm/°C Temperature Drift (typ)

monotonic, provides very good linearity, and

minimizes undesired code-to-code transient voltages

– 5ppm/°C Temperature Drift (max)

(glitch). The DAC7565 uses a versatile 3-wire serial

– 20mA Sink/Source Capability

interface that operates at clock rates up to 50MHz.

• Power-On Reset to Zero-Scale or Mid-Scale

The interface is compatible with standard SPI™,

QSPI™, Microwire™, and digital signal processor

• Asynchronous Clear to Zero-Scale or

(DSP) interfaces.

Mid-Scale

• Ultra-Low Power Operation: 1mA at 5V

The DAC7565 incorporates a power-on-reset circuit

that ensures the DAC output powers up at either

• Wide Power-Supply Range: +2.7V to +5.5V

zero-scale or mid-scale until a valid code is written to

• 12-Bit Monotonic Over Temperature Range

the device. The device contains a power-down

• Settling Time: 10μs to ±0.024% Full-Scale

feature, accessed over the serial interface, that

Range (FSR)

reduces the current consumption of the device to

1.3μA at 5V. Power consumption is 2.9mW at 3V,

• Low-Power Serial Interface with

reducing to 1.5μW in power-down mode. The low

Schmitt-Triggered Inputs: Up to 50MHz

power consumption, internal reference, and small

• On-Chip Output Buffer Amplifier with

footprint make this device ideal for portable,

Rail-to-Rail Operation

battery-operated equipment.

• 1.8V to 5.5V Logic Compatibility

The DAC7565 is drop-in and functionally compatible

• Temperature Range: –40°C to +105°C

with the DAC8165 and DAC8565, and functionally

compatible with the DAC7564, DAC8164 and

APPLICATIONS

DAC8564. All these devices are available in a

TSSOP-16 package.

• Portable Instrumentation

• Closed-Loop Servo-Control

• Process Control, PLCs

• Data Acquisition Systems

• Programmable Attenuation

• PC Peripherals

DEVICES 16-BIT 14-BIT 12-BIT

Pin and

Functionally DAC8565 DAC8165 DAC7565

Compatible

Functionally

DAC8564 DAC8164 DAC7564

Compatible

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI, QSPI are trademarks of Motorola, Inc.

3Microwire is a trademark of National Semiconductor.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (49 pages)

PAGE 1
DA DAC7565 C7 565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com 12-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter with 2.5V, 2ppm/°C Internal Reference Check for Samples: DAC7565 FEATURES DESCRIPTION • Relative Accuracy: 0.5LSB • Glitch Energy: 0.15nV-s • Internal Reference: – 2.5V Reference Voltage (enabled by default) – 0.
PAGE 2
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted). DAC7565 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE (1) Resolution 12 Relative accuracy Measured by the line passing through codes 30 and 4050 Differential nonlinearity 12-bit monotonic DAC7565A, DAC7565C Bits ±0.5 ±1 LSB LSB ±0.1 ±0.
PAGE 4
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted). DAC7565 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE OUTPUT Output voltage TA = +25°C 2.4975 2.5 2.5025 V Initial accuracy TA = +25°C –0.1 ±0.004 0.1 % DAC7565A (3) 5 25 DAC7565C (4) 2 5 Output voltage temperature drift Output voltage noise ppm/°C μVPP f = 0.
PAGE 5
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com PIN CONFIGURATIONS PW PACKAGE TSSOP-16 (Top View) VOUTA 1 16 LDAC VOUTB 2 15 ENABLE VREFH/VREFOUT 3 14 RSTSEL AVDD 4 13 RST DAC7565 VREFL 5 12 IOVDD GND 6 11 DIN VOUTC 7 10 SCLK VOUTD 8 9 SYNC PIN DESCRIPTIONS PIN NAME 1 VOUTA Analog output voltage from DAC A DESCRIPTION 2 VOUTB Analog output voltage from DAC B 3 VREFH/ VREFOUT Positive reference input / reference output 2.5V if internal reference used.
PAGE 6
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.
PAGE 7
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS (1) (2) At AVDD = IOVDD= 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
PAGE 8
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: Internal Reference At TA = +25°C, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (Grade A) 2.503 2.503 2.502 2.502 2.501 2.501 VREF (V) VREF (V) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (Grade C) 2.500 2.499 2.500 2.499 2.498 2.498 10 Units Shown 2.497 -40 -20 0 20 40 60 80 100 13 Units Shown 2.
PAGE 9
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: Internal Reference (continued) At TA = +25°C, unless otherwise noted. INTERNAL REFERENCE NOISE DENSITY vs FREQUENCY INTERNAL REFERENCE NOISE 0.1Hz TO 10Hz 300 250 VNOISE (5mV/div) VN (nV/ÖHz) 12mV (peak-to-peak) 200 Reference Unbuffered CREF = 0mF 150 100 50 CREF = 4.8mF 0 10 100 1k 10k 100k Time (2s/div) 1M Frequency (Hz) Figure 7. Figure 8.
PAGE 10
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) LE (LSB) 0 -0.5 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 13. Figure 14.
PAGE 11
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) LE (LSB) 0 -0.5 -1.0 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 19.
PAGE 12
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. OFFSET ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 4 0.
PAGE 13
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 1400 AVDD = 5.
PAGE 14
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY -40 TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY -40 Channel A, AVDD = 5V, External VREF = 4.
PAGE 15
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 94 Channel C 92 Channel B AVDD = 5V, External VREF = 4.
PAGE 16
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. AVDD = 5V Int VREF = 2.5V From Code: 0800h To Code: 07FFh Glitch: 0.06nV-s Time (5ms/div) Figure 48. Figure 49. GLITCH ENERGY: 5V, 4LSB STEP, RISING EDGE GLITCH ENERGY: 5V, 4LSB STEP, FALLING EDGE AVDD = 5V Int VREF = 2.
PAGE 17
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. DAC OUTPUT NOISE DENSITY vs FREQUENCY (1) 1200 DAC OUTPUT NOISE DENSITY vs FREQUENCY (2) 400 Internal Reference Enabled No Load at VREFH/VREFOUT Pin 1000 DAC = Full-Scale Internal Reference Enabled 4.
PAGE 18
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE POWER-SUPPLY CURRENT vs TEMPERATURE 1400 2400 Power-Supply Current (mA) Power-Supply Current (mA) AVDD = IOVDD = 3.6V, Internal VREF Included SYNC Input (all other digital inputs = GND) 2000 1600 Sweep from 0V to 3.
PAGE 19
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) LE (LSB) 0 -0.5 -1.0 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.
PAGE 20
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) LE (LSB) 0 -1.0 -1.0 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.
PAGE 21
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted OFFSET ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 4 0.50 AVDD = 2.7V Internal VREF Enabled Full-Scale Error (mV) 3 Offset Error (mV) AVDD = 2.
PAGE 22
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 1600 AVDD = 2.7V Internal VREF Included AVDD = 2.
PAGE 23
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted AVDD = 2.7V Int VREF = 2.5V From Code: 07FFh To Code: 0800h Glitch: 0.1nV-s GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE VOUT (500mV/div) VOUT (500mV/div) GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE AVDD = 2.7V Int VREF = 2.
PAGE 24
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 1300 2.0 AVDD = 2.7V Internal VREF Included DAC Loaded with 0800h AVDD = 2.
PAGE 25
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) The DAC7565 architecture consists of a string DAC followed by an output buffer amplifier. Figure 92 shows a block diagram of the DAC architecture. code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier.
PAGE 26
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com INTERNAL REFERENCE VREF The DAC7565 includes a 2.5V internal reference that is enabled by default. The internal reference is externally available at the VREFH/VREFOUT pin. A minimum 100nF capacitor is recommended between the reference output and GND for noise filtering. Reference Disable The internal reference of the DAC7565 is a bipolar transistor-based, precision bandgap voltage reference. Figure 94 shows the basic bandgap topology.
PAGE 27
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com SERIAL INTERFACE The DAC7565 has a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. The DAC7565 input shift register is 24 bits wide, consisting of eight control bits (DB23 to DB16) and 12 data bits (DB15 to DB4).
PAGE 28
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com LD1 (DB21) and LD0 (DB20) control the loading of each analog output with the specified 12-bit data value or power-down command. Bit DB19 must always be '0'. The DAC channel select bits (DB18, DB17) control the destination of the data (or power-down command) from DAC A through DAC D. The final control bit, PD0 (DB16), selects the power-down mode of the DAC7565 channels as well as the power-down mode of the internal reference.
PAGE 29
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com SYNC INTERRUPT LDAC FUNCTIONALITY In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed DAC register updates on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded.
PAGE 30
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com POWER-DOWN MODES The DAC7565 has two separate sets of power-down commands. One set is for the DAC channels and the other set is for the internal reference. For more information on powering down the reference, see the Enable/Disable Internal Reference section. DAC Power-Down Commands The DAC7565 uses four modes of operation. These modes are accessed by setting three bits (PD2, PD1, and PD0) in the shift register.
PAGE 31
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com OPERATING EXAMPLES: DAC7565 For the following examples, X = don't care; value can be either '0' or '1'.
PAGE 32
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ Simultaneously • 1st: Write power-down command to data buffer A: DAC A to 1kΩ.
PAGE 33
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.
PAGE 34
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION INTERNAL REFERENCE The internal reference of the DAC7565 does not require an external load capacitor for stability because it is stable with any capacitive load. However, for improved noise performance, an external load capacitor of 150nF or larger connected to the VREFH/VREFOUT output is recommended. Figure 97 shows the typical connections required for operation of the DAC7565 internal reference.
PAGE 35
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com Load Regulation Thermal Hysteresis Load regulation is defined as the change in reference output voltage as a result of changes in load current. The load regulation of the internal reference is measured using force and sense contacts as shown in Figure 98. The force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of the load regulation contributed solely by the internal reference.
PAGE 36
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com BIPOLAR OPERATION USING THE DAC7565 The DAC7565 is designed for single-supply operation, but a bipolar output range is also possible using the circuit in either Figure 99 or Figure 100. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.
PAGE 37
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com DAC7565 to Microwire Interface MICROPROCESSOR INTERFACING DAC SPI Interfacing Care must be taken with the digital control signals that are applied directly to the DAC, especially with the SYNC pin. The SYNC pin must not be toggled without having a full SCLK pulse in between. If this condition is violated, the SPI interface locks up in an erroneous state, causing the DAC to behave incorrectly and have errors.
PAGE 38
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC7565 offers single-supply operation, and is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors.
PAGE 39
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this section summarizes selected specifications related to digital-to-analog converters. STATIC PERFORMANCE Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and provide information on the accuracy of the DAC.
PAGE 40
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com Power-Supply Rejection Ratio (PSRR) Channel-to-Channel DC Crosstalk Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is measured in decibels (dB).
PAGE 41
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com DAC Output Noise Density Full-Scale Range (FSR) Output noise density is defined as internally-generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output.
PAGE 42
DAC7565 SBAS412B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2008) to Revision B Page • Changed Output Voltage parameter min/max values from 2.4995 and 2.5005 to 2.4975 and 2.5025, respectively ........... 4 • Changed Initial Accuracy parameter min/max values from –0.02 and 0.02 to –0.1 and 0.1, respectively ...........................
PAGE 43
PACKAGE OPTION ADDENDUM www.ti.
PAGE 44
PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 45
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7565IAPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC7565ICPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 46
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7565IAPWR TSSOP PW 16 2000 367.0 367.0 35.0 DAC7565ICPWR TSSOP PW 16 2000 367.0 367.0 35.
PAGE 47
PAGE 48
PAGE 49
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.