Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOT 23 6

www.ti.com

FEATURES DESCRIPTION

APPLICATIONS

SCLA0

GND

Output

Buffer

Power Down

Control Logic

Resistor

Network

Ref (+) REF(-)

12-Bit

DAC

Control

Logic

DAC

Power-On

Reset

OUT

SDA

DAC7571

SLAS374C – FEBRUARY 2003 – REVISED MAY 2006

+2.7 V to +5.5 V, I

C INTERFACE (RECEIVE ONLY), VOLTAGE OUTPUT,

12-BIT DIGITAL-TO-ANALOG CONVERTER

• Micropower Operation: 140 µA @ 5 V

The DAC7571 is a low-power, single channel, 12-bit

• Power-On Reset to Zero

buffered voltage output DAC. Its on-chip precision

output amplifier allows rail-to-rail output swing to be

• +2.7-V to +5.5-V Power Supply

achieved. The DAC7571 utilizes an I

C compatible

• Specified Monotonic by Design

two wire serial interface that operates at clock rates

• Settling Time: 10 µs to ±0.003%FS

up to 3.4 Mbps with address support of up to two

• I

C™ Interface up to 3.4 Mbps

DAC7571s on the same data bus.

• On-Chip Output Buffer Amplifier, Rail-to-Rail

The output voltage range of the DAC is set to V

Operation

The DAC7571 incorporates a power-on-reset circuit

• Double-Buffered Input Register

that ensures that the DAC output powers up at zero

• Address Support for up to Two DAC7571s

volts and remains there until a valid write to the

device takes place. The DAC7571 contains a

• Small 6-Lead SOT Package

power-down feature, accessed via the internal

• Operation From –40 °C to 105 °C

control register, that reduces the current

consumption of the device to 50 nA at 5 V.

The low power consumption of this part in normal

• Process Control

operation makes it ideally suited for portable battery

• Data Acquistion Systems

operated equipment. The power consumption is less

• Closed-Loop Servo Control

than 0.7 mW at V

= 5 V reducing to 1 µW in

• PC Peripherals

power-down mode.

• Portable Instrumentation

The DAC7571 is available in a 6-lead SOT 23

package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

I2C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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D AC 7 512 DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 +2.7 V to +5.5 V, I2C INTERFACE (RECEIVE ONLY), VOLTAGE OUTPUT, 12-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • • • • • • • The DAC7571 is a low-power, single channel, 12-bit buffered voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC7571 utilizes an I2C compatible two wire serial interface that operates at clock rates up to 3.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 ELECTRICAL CHARACTERISTICS (continued) VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted. PARAMETER CONDITIONS DAC7571 MIN Zero code error Full-scale error All ones loaded to DAC register TYP MAX UNITS 5 20 mV –0.15 –1.25 % of FSR ±1.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 TIMING CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS fSCL SCL Clock Frequency MIN MAX UNITS Standard mode 100 kHz Fast mode 400 kHz High-speed mode, CB - 100pF max 3.4 MHz 1.7 MHz High-Speed mode, CB - 400pF max tBUF tHD; tSTA tLOW tHIGH tSU; tSTA tSU; tDAT tHD; tDAT tRCL Bus Free Time Between a STOP and START Condition Standard mode 4.7 µs Fast mode 1.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 TIMING CHARACTERISTICS (continued) SYMBOL PARAMETER TEST CONDITIONS tSU; tSTO Setup Time for STOP Condition Standard mode 4.0 µs Fast mode 600 ns High-speed mode 160 ns CB Capacitive Load for SDA and SCL tSP Pulse Width of Spike Suppressed VNH Noise Margin at the HIGH Level for Each Connected Device (Including Hysteresis) MIN TYP MAX UNITS 400 pF Fast mode 50 ns High-speed mode 10 ns Standard mode 0.2VDD V 0.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. FULL-SCALE ERROR vs TEMPERATURE 30 30 20 20 Zero-Scale Error − mV Zero-Scale Error − mV ZERO-SCALE ERROR vs TEMPERATURE 10 0 −10 10 0 −10 −20 −20 −30 −50 −30 −10 10 30 50 T − Temperature − _C 70 90 −30 −50 110 −30 10 30 50 T − Temperature − _C 70 90 110 Figure 5. Figure 6.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. SUPPLY CURRENT vs SUPPLY VOLTAGE POWER-DOWN CURRENT vs SUPPLY VOLTAGE 300 90 80 200 70 150 IDD (nA) I DD − Supply Current − µ A 100 250 100 60 +105°C 50 –40°C 40 30 50 20 0 2.7 3.2 3.7 4.2 4.7 VDD − Supply Voltage − V 5.2 5.7 +25°C 10 0 2.7 3.2 3.7 4.2 4.7 5.2 5.7 VDD (V) Figure 11. Figure 12.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME HALF-SCALE SETTLING TIME CLK (5V/div) CLK (5V/div) VOUT (1V/div) Full-Scale Code Change FFFH to 000H Output Loaded with 2kΩ and 200pF to GND Half-Scale Code Change 400H to C00H Output Loaded with 2kΩ and 200pF to GND VOUT (1V/div) Time (1µs/div) Time (1µs/div) Figure 15. Figure 16.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VDD = +2.7 V At TA = +25°C, +VDD = +2.7V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25 °C) LE − LSB 8 6 4 2 0 −2 −4 −6 −8 8 6 4 2 0 −2 −4 −6 −8 1 1 0.5 0.5 DLE − LSB DLE − LSB LE − LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40 °C) 0 −0.5 −1 0 512 1024 1536 2048 2560 3072 3584 0 −0.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7V, unless otherwise noted. IDD HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY SOURCE AND SINK CURRENT CAPABILITY 2500 3 VDD = +3V DAC Loaded with FFFH 2 1500 VOUT (V) f − Frequency − Hz 2000 1000 1 500 190 200 180 160 170 140 150 130 110 120 90 100 80 DAC Loaded with 000H 0 0 IDD − Supply Current − mA 0 5 10 15 ISOURCE/SINK (mA) Figure 27.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7V, unless otherwise noted. FULL SCALE SETTLING TIME HALF SCALE SETTLING TIME CLK (2.7V/div) CLK (2.7V/div) Full-Scale Code Change FFFH to 000H Output Loaded with 2kΩ and 200pF to GND VOUT (1V/div) VOUT (1V/div) Time (1µs/div) Half-Scale Code Change 400H to C00H Output Loaded with 2kΩ and 200pF to GND Time (1µs/div) Figure 33. Figure 34.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 THEORY OF OPERATION D/A SECTION The architecture of the DAC7571 consists of a string DAC followed by an output buffer amplifier. Figure 39 shows a block diagram of the DAC architecture. VDD REF (+) Resistor String DAC Register VOUT Output Amplifier REF (-) GND Figure 39.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 THEORY OF OPERATION (continued) OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0 V to VDD. It is capable of driving a load of 2kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics. The slew rate is 1V/µs with a half-scale settling time of 8 µs with the output unloaded.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 THEORY OF OPERATION (continued) SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 43. Bit Transfer on the I2C Bus • When all data bits have been written, a Stop condition is established (see Figure 44). In writing to the DAC7571, the master must pull the SDA line high during the tenth clock pulse to establish a Stop condition.
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DAC7571 www.ti.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 MASTER TRANSMITTER WRITING TO A SLAVE RECEIVER (DAC7571) IN STANDARD/FAST MODES I2C protocol starts when the bus is dile, that is, when SDA and SCL lines are stable high. The master then pulls the SDA line low while SCL is still high indicting that serial data transfer has started. This is called a start condition, and can only be asserted by the master.
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 Table 2. Modes of Operation for the DAC7571 PD1 PD0 0 0 OPERATING MODE Normal Operation 0 1 1kΩ to AGND, PWD 1 0 100kΩ to AGND, PWD 1 1 High Impedance, PWD When both bits are set to 0, the device works normally with normal power consumption of 150 µA at 5V. However, for the three power-down modes, the supply current falls to 200 nA at 5V (50 nA at 3 V).
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DAC7571 www.ti.com SLAS374C – FEBRUARY 2003 – REVISED MAY 2006 APPLICATIONS USING REF02 AS A POWER SUPPLY FOR THE DAC7571 Due to the extremely low supply current required by the DAC7571, a possible configuration is to use a REF02 +5V precision voltage reference to supply the required voltage to the DAC7571's supply input as well as the reference input, as shown in Figure 47. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DAC7571IDBVR SOT-23 DBV 6 3000 178.0 9.0 DAC7571IDBVT SOT-23 DBV 6 250 178.0 9.0 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7571IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 DAC7571IDBVT SOT-23 DBV 6 250 180.0 180.0 18.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.