Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VSSOP 10

www.ti.com

Resistor

Network

Data

Buffer A

DAC

Data

Buffer D

DAC

DAC A

DAC D

Buffer

Control

Power-Down

Control Logic

OUT

A0 A1 GND

C Block

SCL

SDA

DAC7574

SLAS375–JUNE 2003

QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT,

C INTERFACE DIGITAL-TO-ANALOG CONVERTER

FEATURES DESCRIPTION

• Micropower Operation: 600 µA at 5 V V

The DAC7574 is a low-power, quad channel, 12-bit

• Power-On Reset to Zero buffered voltage output DAC. Its on-chip precision out-

put amplifier allows rail-to-rail output swing to be

• +2.7 V to +5.5 V Analog Power Supply

achieved. The DAC7574 utilizes an I

C compatible two

• 12-Bit Monotonic

wire serial interface supporting high-speed interface

• I

C™ Interface Up to 3.4 Mbps

mode with address support of up to four DAC7574s for

a total of 16 channels on the bus.

• Data Transmit Capability

• On-Chip Output Buffer Amplifier, Rail-to-Rail

The DAC7574 uses V

and GND to set the output

Operation

range of the DAC. The DAC7574 incorporates a

• Double-Buffered Input Register

power-on-reset circuit that ensures that the DAC output

powers up at zero volts and remains there until a valid

• Address Support for up to Four DAC7574s

write takes place to the device. The DAC7574 contains

• Synchronous Update Support for up to 16

a power-down feature, accessed via the internal control

Channels

• Operation From -40°C to 105°C

device to 200 nA at 5 V.

• Small 10 Lead MSOP Package

The low power consumption of this part in normal

operation makes it ideally suited to portable battery

APPLICATIONS

operated equipment. The power consumption is less

• Process Control

than 3mW at V

= 5 V reducing to 1 µW in power-down

mode.

• Data Acquisition Systems

The DAC7574 is available in a 10-lead MSOP package.

• Closed-Loop Servo Control

• PC Peripherals

• Portable Instrumentation

I2C is a trademark of Philips Corporation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily in-

cludetesting of all parameters.

Summary of content (36 pages)

PAGE 1
DAC7574 www.ti.com SLAS375 – JUNE 2003 QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I C INTERFACE DIGITAL-TO-ANALOG CONVERTER 2 FEATURES DESCRIPTION • • • • • • • The DAC7574 is a low-power, quad channel, 12-bit buffered voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved.
PAGE 2
DAC7574 www.ti.com SLAS375 – JUNE 2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
DAC7574 www.ti.com SLAS375 – JUNE 2003 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified. PARAMETER STATIC PERFORMANCE (1) TEST CONDITIONS Resolution MIN TYP MAX UNITS ±8 LSB ±1 LSB 12 Bits Relative accuracy Differential nonlinearity Specified monotonic by design Zero-scale error 5 20 mV Full-scale error -0.15 ±1.0 % of FSR ± 1.
PAGE 4
DAC7574 www.ti.com SLAS375 – JUNE 2003 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS +105 °C TEMPERATURE RANGE Specified performance -40 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.
PAGE 5
DAC7574 www.ti.com SLAS375 – JUNE 2003 TIMING CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.
PAGE 6
DAC7574 www.ti.com SLAS375 – JUNE 2003 TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. 8 6 4 2 0 -2 -4 -6 -8 Channel A VDD = 5 V LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LE - LSB LE - LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.5 0.0 - 0.5 - 1.0 0.5 0.0 - 0.5 512 1024 1536 2048 2560 3072 3584 0 2048 2560 Figure 2.
PAGE 7
DAC7574 www.ti.com SLAS375 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. Channel C VDD = 2.7 V LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LE - LSB LE - LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 8 6 4 2 0 -2 -4 -6 -8 Channel D 0.5 0.0 - 0.5 - 1.0 0.5 0.0 - 0.5 - 1.0 0 512 1024 1536 2048 2560 3072 3584 0 512 1024 1536 2560 Digital Input Code Figure 7. Figure 8.
PAGE 8
DAC7574 www.ti.com SLAS375 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SINK CURRENT CAPABILITY AT NEGATIVE RAIL SOURCE CURRENT CAPABILITY AT POSITIVE RAIL 0.150 5.50 Typical For All Channels 0.100 VOUT - Output Voltage - V VOUT - Output Voltage - V Typical For All Channels 0.125 VDD = 2.7 V VDD = 5.5 V 0.075 0.050 0.025 5.45 5.40 5.35 DAC Loaded With FFFH VDD = 5.5 V DAC Loaded With 000H 0.000 5.
PAGE 9
DAC7574 www.ti.com SLAS375 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION 2000 TA = 25°C SCL Input (All Other Inputs = GND) VDD = 5 V 1000 1500 Frequency IDD - Supply Current - µA 1200 800 VDD = 5.5 V 600 1000 500 400 VDD = 2.7 V 200 0 0 1 2 3 4 500 520 540 560 580 600 620 640 660 680 700 720 740 5 IDD - Current Consumption - µA VLogic - Logic Input Voltage - V Figure 19.
PAGE 10
DAC7574 www.ti.com SLAS375 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. ABSOLUTE ERROR ABSOLUTE ERROR 24 18 VDD = 5 V TA = 25°C 14 Channel A Output 16 12 8 Channel C Output Output Error - mV Output Error - mV 20 Channel B Output 10 6 2 -6 0 512 1024 1536 2048 2560 3072 3584 0 Figure 25. 1024 1536 2048 2560 Figure 26. LARGE SIGNAL SETTLING TIME LARGE SIGNAL SETTLING TIME 3.
PAGE 11
DAC7574 www.ti.com SLAS375 – JUNE 2003 THEORY OF OPERATION D/A SECTION The architecture of the DAC7574 consists of a string DAC followed by an output buffer amplifier. Figure 29 shows a generalized block diagram of the DAC architecture. VDD 50 k 50 k 70 k _ Ref+ Resistor String Ref- DAC Register + VOUT GND Figure 29.
PAGE 12
DAC7574 SLAS375 – JUNE 2003 www.ti.com THEORY OF OPERATION (continued) The DAC7574 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode.
PAGE 13
DAC7574 www.ti.com SLAS375 – JUNE 2003 THEORY OF OPERATION (continued) SDA SDA SCL SCL S P Start Condition Stop Condition Figure 31. START and STOP Conditions SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 32. Bit Transfer on the I2C Bus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 S 8 9 Clock Pulse for Acknowledgement START Condition Figure 33.
PAGE 14
DAC7574 www.ti.com SLAS375 – JUNE 2003 Recognize STOP or REPEATED START Condition Recognize START or REPEATED START Condition Generate ACKNOWLEDGE Signal P SDA MSB Acknowledgement Signal From Slave Sr Address R/W SCL S or Sr 1 2 7 8 9 ACK 1 2 3-8 9 ACK Sr or P Clock Line Held Low While Interrupts are Serviced START or Repeated START Condition STOP or Repeated START Condition Figure 34.
PAGE 15
DAC7574 www.ti.com SLAS375 – JUNE 2003 Broadcast Address Byte MSB LSB 1 0 0 1 0 0 0 0 Broadcast addressing is also supported by DAC7574. Broadcast addressing can be used for synchronously updating or powering down multiple DAC7574 devices. DAC7574 is designed to work with other members of the DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address, DAC7574 responds regardless of the states of the address pins.
PAGE 16
DAC7574 www.ti.com SLAS375 – JUNE 2003 Table 2. Control Byte C7 0 C6 0 C5 C4 C3 Load1 Load0 Don’t Care C2 Ch Sel 1 0 0 X 0 0 0 0 C1 C0 MSB7 MSB6 MSB5... Ch Sel 0 PD0 MSB (PD1) MSB-1 (PD2) MSB-2 ...
PAGE 17
DAC7574 www.ti.com SLAS375 – JUNE 2003 LDAC Functionality Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four DAC output voltages to be updated simultaneously with temporary register data.
PAGE 18
DAC7574 www.ti.com SLAS375 – JUNE 2003 DAC7574 as a Slave Receiver - High-Speed Mode Figure 36 shows the high-speed mode master transmitter addressing a DAC7574 Slave Receiver with a 7-bit address.
PAGE 19
DAC7574 www.ti.com SLAS375 – JUNE 2003 Master Transmitter Writing to a Slave Receiver (DAC7574) in Standard/Fast Modes All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This control byte specifies the operation mode of DAC7574 and determines which channel of DAC7574 is being accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the following data is power-down data or regular data.
PAGE 20
DAC7574 www.ti.com SLAS375 – JUNE 2003 Master Transmitter Writing to a Slave Receiver (DAC7574) in HS Mode When writing data to the DAC7574 in HS-mode, the master begins to transmit what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge.
PAGE 21
DAC7574 www.ti.com SLAS375 – JUNE 2003 DAC7574 as a Slave Transmitter - Standard and Fast Mode Figure 37 shows the standard and fast mode master transmitter addressing a DAC7574 Slave Transmitter with a 7-bit address.
PAGE 22
DAC7574 www.ti.com SLAS375 – JUNE 2003 Master Receiver Reading From a Slave Transmitter (DAC7574) in Standard/Fast Modes When reading data back from the DAC7574, the user begins with an address byte (with R/W = 0) after which the DAC7574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which is also acknowledged by the DAC7574. Following this there is a REPEATED START condition by the Master and the address is resent with (R/W = 1).
PAGE 23
DAC7574 www.ti.com SLAS375 – JUNE 2003 Master Receiver Reading From a Slave Transmitter (DAC7574) in HS-Mode When reading data to the DAC7574 in HS-MODE, the master begins to transmit, what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge.
PAGE 24
DAC7574 www.ti.com SLAS375 – JUNE 2003 Power-Down Modes The DAC7574 contains four separate power-down modes of operation. The modes are programmable via two most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits correspond to the mode of operation of the device. Table 8.
PAGE 25
www.ti.com DAC7574 SLAS375 – JUNE 2003 DRIVING RESISTIVE AND CAPACITIVE LOADS The DAC7574 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset and gain error margins, the DAC7574 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2 kΩ can be driven by the DAC7574 while achieving a typical load regulation of 1%. As the load resistance drops below 2 kΩ, the load regulation error increases.
PAGE 26
DAC7574 www.ti.com SLAS375 – JUNE 2003 APPLICATION INFORMATION The following sections give example circuits and tips for using the DAC7574 in various applications. For more information, contact your local TI representative, or visit the Texas Instruments website at http://www.ti.com. BASIC CONNNECTIONS For many applications, connecting the DAC7574 is extremely simple. A basic connection diagram for the DAC7574 is shown in Figure 40. The 0.
PAGE 27
DAC7574 www.ti.com SLAS375 – JUNE 2003 APPLICATION INFORMATION (continued) DAC7574 VDD 1 VOUTA A1 10 2 VOUTB A0 9 3 GND VDD 8 4 VOUTC SDA 7 5 VOUTD SCL 6 Microcontroller or Microprocessor GPIO-1 GPIO-2 NOTE: DAC7574 power and input/output connections are omitted for clarity, except I C Inputs. Figure 41.
PAGE 28
DAC7574 www.ti.com SLAS375 – JUNE 2003 APPLICATION INFORMATION (continued) POWER SUPPLY REJECTION The positive reference voltage input of DAC7574 is internally tied to the power supply pin of the device. This increases I2C system flexibility, creating room for an extra I2C address pin in a low pin-count package. To eliminate the supply noise appearing at the DAC output, the user must pay close attention to how DAC7574 is powered. The supply to DAC7574 must be clean and well regulated.
PAGE 29
www.ti.com DAC7574 SLAS375 – JUNE 2003 As with the GND connection, VDD should be connected to a positive power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a 1 µF to 10 µF capacitor in parallel with a 0.1 µF bypass capacitor is strongly recommended.
PAGE 30
PACKAGE OPTION ADDENDUM www.ti.
PAGE 31
PACKAGE OPTION ADDENDUM www.ti.
PAGE 32
PACKAGE MATERIALS INFORMATION www.ti.com 19-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC7574IDGSR Package Package Pins Type Drawing VSSOP DGS 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
PAGE 33
PACKAGE MATERIALS INFORMATION www.ti.com 19-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7574IDGSR VSSOP DGS 10 2500 367.0 367.0 35.
PAGE 34
PAGE 35
PAGE 36
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.