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DAC7624/7625

12-Bit Quad Voltage Output

DIGITAL-TO-ANALOG CONVERTER

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DAC7624

DAC7625

DESCRIPTION

The DAC7624 and DAC7625 are 12-bit quad voltage

output digital-to-analog converters with guaranteed 12-

bit monotonic performance over the specified tempera-

ture range. They accept 12-bit parallel input data, have

double-buffered DAC input logic (allowing simulta-

neous update of all DACs), and provide a readback

mode of the internal input registers. An asynchronous

reset clears all registers to a mid-scale code of 800

(DAC7624) or to a zero-scale of 000

(DAC7625). The

DAC7624 and DAC7625 can operate from a single +5V

supply or from +5V and –5V supplies.

Low power and small size per DAC make the DAC7624

and DAC7625 ideal for automatic test equipment,

DAC-per-pin programmers, data acquisition systems,

and closed-loop servo-control. The DAC7624 and

DAC7625 are available in a 28-pin plastic double-

wide or a 28-lead SOIC package, and offer guaranteed

specifications over the –40°C to +85°C temperature

range.

FEATURES

● LOW POWER: 20mW

● UNIPOLAR OR BIPOLAR OPERATION

● SETTLING TIME: 10µs to 0.012%

● 12-BIT LINEARITY AND MONOTONICITY:

–40°C to +85°C

● RESET TO MID-SCALE (DAC7624) OR

ZERO-SCALE (DAC7625)

● DATA READBACK

● DOUBLE-BUFFERED DATA INPUTS

APPLICATIONS

● PROCESS CONTROL

● ATE PIN ELECTRONICS

● CLOSED-LOOP SERVO-CONTROL

● MOTOR CONTROL

● DATA ACQUISITION SYSTEMS

● DAC-PER-PIN PROGRAMMERS

DAC7624

DAC7625

DAC A

DAC

Input

I/O

Buffer

Control

Logic

DAC B

DAC

Input

DAC C

DAC

Input

DAC D

DAC

Input

REFH

OUTD

OUTC

OUTB

OUTA

REFLRESET LDAC

GND

R/W

DB0-DB11

SBAS083

Summary of content (17 pages)

PAGE 1
DAC7624 DAC7625 ® DAC 762 4 DAC 762 5 12-Bit Quad Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● LOW POWER: 20mW The DAC7624 and DAC7625 are 12-bit quad voltage output digital-to-analog converters with guaranteed 12bit monotonic performance over the specified temperature range. They accept 12-bit parallel input data, have double-buffered DAC input logic (allowing simultaneous update of all DACs), and provide a readback mode of the internal input registers.
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SPECIFICATION At TA = –40°C to +85°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, unless otherwise noted.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VDD to VSS ............................................................................. –0.3V to 11V VDD to GND .......................................................................... –0.3V to 5.5V VREFL to VSS .............................................................. –0.3V to (VDD – VSS) VDD to VREFH ............................................................. –0.3V to (VDD – VSS) VREFH to VREFL .....................................
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PIN CONFIGURATIONS Top View DIP SOIC VREFH 1 28 VREFL VREFH 1 28 VREFL VOUTB 2 27 VOUTC VOUTB 2 27 VOUTC VOUTA 3 26 VOUTD VOUTA 3 26 VOUTD VSS 4 25 VDD VSS 4 25 VDD GND 5 24 NIC GND 5 24 NIC RESET 6 23 CS RESET 6 23 CS LDAC 7 22 A0 LDAC 7 22 A0 (LSB) DB0 8 21 A1 (LSB) DB0 8 21 A1 DB1 9 20 R/W DB1 9 20 R/W DB2 10 19 DB11 (MSB) DB2 10 19 DB11 (MSB) DB3 11 18 DB10 DB3 11 18 DB10 DB4 12 17 DB9 DB4 12 17 DB9 DB5 13 16 D
PAGE 5
TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. 0.50 0.25 0.25 LE (LSB) 0.50 0.00 –0.25 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H A00H C00H 0.25 0.00 –0.25 –0.50 000H E00H FFFH 600H 800H A00H C00H E00H FFFH LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D) 0.25 LE (LSB) 0.50 0.25 0.00 –0.
PAGE 6
TYPICAL PERFORMANCE CURVES: VSS = 0V (CONT) At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. LINEARITY ERROR vs CODE (DAC D, –40°C and +85°C) 0.50 0.50 0.25 0.25 LE (LSB) LE (LSB) LINEARITY ERROR vs CODE (DAC C, –40°C and +85°C) 0.00 –0.25 0.00 –0.25 +85°C 0.50 0.50 0.25 0.25 LE (LSB) –0.50 0.00 –0.25 –40°C –0.50 000H 200H 6 400H 600H 800H A00H C00H 0.00 –0.25 –40°C –0.
PAGE 7
TYPICAL PERFORMANCE CURVES: VSS = –5V At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. 0.50 0.25 0.25 LE (LSB) 0.50 0.00 –0.25 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H A00H C00H 0.25 0.00 –0.25 –0.50 000H E00H FFFH 600H 800H A00H C00H E00H FFFH LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D) 0.25 LE (LSB) 0.50 0.25 0.00 –0.
PAGE 8
TYPICAL PERFORMANCE CURVES: VSS = –5V (CONT) At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. LINEARITY ERROR vs CODE (DAC D, –40°C and +85°C) 0.50 0.50 0.25 0.25 LE (LSB) LE (LSB) LINEARITY ERROR vs CODE (DAC C, –40°C and +85°C) 0.00 –0.25 0.00 –0.25 +85°C 0.50 0.50 0.25 0.25 LE (LSB) –0.50 0.00 –0.25 Zero-Scale Error (LSB) –40°C –0.50 000H 200H 400H 600H 800H A00H C00H 0.00 –0.25 –40°C –0.
PAGE 9
THEORY OF OPERATION are set by the external voltage references (VREFL and VREFH, respectively). The digital input is a 12-bit parallel word and the DAC input registers offer a readback capability. The converters can be powered from a single +5V supply or a dual ±5V supply. Each device offers a reset function which immediately sets all DAC output voltages and DAC registers to mid-scale (DAC7624, code 800H) or to zero-scale (DAC7625, code 000H). See Figures 1 and 2 for the basic operation of the DAC7624/25.
PAGE 10
ANALOG OUTPUTS The current into the VREFH input depends on the DAC output voltages and can vary from a few microamps to approximately 0.5 milliamp. The VREFH source will not be required to sink current, only source it. Bypassing the reference voltage or voltages with at least a 0.1uF capacitor placed as close to the DAC7624/25 package is strongly recommended. When VSS = –5V (dual supply operation), the output amplifier can swing to within 2.
PAGE 11
DIGITAL TIMING DIGITAL INPUT CODING Figure 3 and Table II provide detailed timing for the digital interface of the DAC7624 and DAC7625. The DAC7624 and DAC7625 input data is in straight binary format. The output voltage is given by the following equation: – V REFL ) • N (V V OUT = V REFL + REFH 4096 where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 13-Jul-2012 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7624U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 DAC7624UB/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 DAC7625U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7624U/1K SOIC DW 28 1000 367.0 367.0 55.0 DAC7624UB/1K SOIC DW 28 1000 367.0 367.0 55.0 DAC7625U/1K SOIC DW 28 1000 367.0 367.0 55.0 DAC7625UB/1K SOIC DW 28 1000 367.0 367.0 55.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.