Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VQFN 24

DAC7678

Data Buffer A

DAC Register A

Buffer Control Register Control

Control Logic

Input Control Logic

Power-Down

Control Logic

REFIN REFOUT

12-Bit DAC

CLRLDACADDR0

SDA

SCL

2.5V

Reference

Data Buffer B

DAC Register B

Data Buffer C

Data Buffer D

Data Buffer E

Data Buffer F

Data Buffer G

DAC Register C

DAC Register D

DAC Register E

DAC Register F

DAC Register G

V H

OUT

Data Buffer H

DAC Register H

V G

OUT

V F

OUT

V E

OUT

V D

OUT

V C

OUT

V B

OUT

V A

OUT

GNDADDR1

12-Bit DAC

RSTSEL

DAC7678

www.ti.com

SBAS493B –FEBRUARY 2010–REVISED JULY 2012

12-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output, Two-Wire Interface

Digital-to-Analog Converter with 2.5V Internal Reference

Check for Samples: DAC7678

FEATURES

APPLICATIONS

• Relative Accuracy:

• Portable Instrumentation

– 1 LSB INL • Closed-Loop Servo-Control

• Glitch Energy: 0.15nV-s • Process Control

• Internal Reference: • Data Acquisition Systems

– 2.5V Reference Voltage (disabled by • Programmable Attenuation

default)

• PC Peripherals

– ±5mV Initial Accuracy (max)

DESCRIPTION

– 5ppm/°C Temperature Drift (typ)

The DAC7678 is a low-power, voltage-output, octal

– 25ppm/°C Temperature Drift (max)

channel, 12-bit digital-to-analog converter (DAC). The

– 20mA Sink/Source Capability

DAC7678 includes a 2.5V internal reference (disabled

• Power-On Reset to Zero Scale or Midscale

by default), giving a full-scale output voltage range of

5V. The internal reference has an initial accuracy of

– Devices in the TSSOP Package Reset to

±5mV and can source up to 20mA at the

Zero Scale

REFIN

REFOUT

pin. The device is monotonic,

– Devices in the QFN Package Reset to Zero

provides very good linearity, and minimizes undesired

Scale or Midscale

code-to-code transient voltages (glitch).

• Ultra-Low Power Operation: 0.13mA/Channel

The DAC7678 uses a versatile, 2-wire serial interface

at 5V (without internal reference current)

that is I

C-compatible and operates at clock rates of

• Wide Power-Supply Range: +2.7V to +5.5V

up to 3.4MHz. Multiple devices can share the same

bus.

• 2-Wire Serial Interface ( I

C™ compatible)

• On-Chip Output Buffer Amplifier with Rail-to-

The DAC7678 incorporates a power-on-reset circuit

that ensures the DAC output powers up to either

Rail Operation

zero-scale or mid-scale until a valid code is written to

• Temperature Range: –40°C to +125°C

the device. These devices contain a power-down

feature, accessed over the serial interface that

reduces the current consumption of the device to

typically 0.42μA at 5V. Power consumption (including

internal reference) is typically 3.56mW at 3V,

reducing to 0.68μW in power-down mode. The low

power consumption, internal reference, and small

footprint make this device ideal for portable, battery-

operated equipment. The DAC7678 is drop-in and

functionally compatible with DAC5578, DAC6578,

and DAC7578. All devices are available in a 4x4

QFN-24 package and a TSSOP-16 package.

RELATED DEVICES 8-BIT 10-BIT 12-BIT

Pin- and Function-Compatible

— — DAC7678

(w/internal reference)

Pin- and Function-Compatible DAC5578 DAC6578 DAC7578

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C is a trademark of NXP Semiconductors.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (53 pages)

PAGE 1
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 12-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output, Two-Wire Interface Digital-to-Analog Converter with 2.5V Internal Reference Check for Samples: DAC7678 FEATURES APPLICATIONS • • • • • • • 1 23 • • • • • • • • Relative Accuracy: – 1 LSB INL Glitch Energy: 0.15nV-s Internal Reference: – 2.
PAGE 2
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 ELECTRICAL CHARACTERISTICS At AVDD = 2.7V to 5.5V, External Reference Used, and over –40°C to +125°C, unless otherwise noted. PARAMETER TEST CONDITIONS DAC7678 MIN TYP MAX UNIT STATIC PERFORMANCE (1) Resolution 12 Bits Relative accuracy Measured by the line passing through codes 30 and 4050 ±0.3 ±1 LSB Differential nonlinearity 12-bit monotonic ±0.1 ±0.25 LSB Offset error Extrapolated from two-point line (2), unloaded 0.
PAGE 4
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At AVDD = 2.7V to 5.5V, External Reference Used, and over –40°C to +125°C, unless otherwise noted. PARAMETER DAC7678 TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE Output voltage TA = +25°C 2.495 2.5 2.505 Initial accuracy TA = +25°C –5 ±0.1 5 mV 5 25 ppm/°C Output voltage temperature drift (4) Output voltage noise TA = +25°C, f = 0.
PAGE 5
DAC7678 www.ti.
PAGE 6
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TIMING DIAGRAM tLOW Low Byte Ack Cycle tR tHD:STA tF SCL tHD:STA tHIGH tSU:STA tSU:STO tSU:DAT tHD:DAT SDA tBUF P S S P t1 LDAC1 t3 t2 LDAC2 t4 CLR (1) Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section (2) Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section Figure 1. Serial Write Operation TIMING REQUIREMENTS At AVDD = 2.
PAGE 7
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: INTERNAL REFERENCE At TA = 25°C, unless otherwise noted INTERNAL REFERENCE VOLTAGE vs TEMPERATURE LONG-TERM STABILITY DRIFT 2.505 2.504 250 22 Devices Shown 150 2.502 100 2.501 Drift - ppm Reference Voltage - V 19 Devices Shown 200 2.503 2.500 2.499 50 0 -50 2.498 -100 2.497 -150 2.496 -200 2.
PAGE 8
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 channels) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 channels) 0.25 1.0 All Eight Channels Shown, AVDD = 5.5 V, Internal Reference = 2.5 V 0.8 0.6 0.15 0.10 DNL - Error - LSB INL - Error - LSB 0.4 0.
PAGE 9
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted LINEARITY ERROR vs DIGITAL INPUT CODE (+125°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+125°C) 0.25 1.00 AVDD = 5.5 V, 0.80 Internal Reference = 2.5 V, Typical Channel Shown 0.60 0.15 0.10 DNL - Error - LSB INL - Error - LSB 0.40 0.
PAGE 10
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER SUPPLY CURRENT vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 0.20 2.20 AVDD = 5.5 V, Internal Reference = 2.5 V 0.15 2.00 1.90 1.80 1.70 1.60 1.50 0.05 0.00 -0.05 -0.10 DAC A DAC C DAC E DAC G -0.15 1.40 1.
PAGE 11
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 5.00 0.60 Channel D 0.50 AVDD = 5.5 V, Internal Reference Enabled, DAC Loaded with 000h Channel D Output Voltage - V Output Voltage - V 4.95 4.90 0.40 0.30 0.20 4.85 AVDD = 5.
PAGE 12
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER SUPPLY CURRENT vs POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT vs POWER SUPPLY VOLTAGE 2.20 1.40 AVDD = 2.7 V to 5.5 V, Internal Reference Enabled AVDD = 2.7 V to 5.5 V, Internal Reference Disabled 1.
PAGE 13
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT HISTOGRAM 14 AVDD = 5.5 V, 12 External Reference = 5 V % of Population 10 8 6 4 2 0.90 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 1.14 1.
PAGE 14
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted CLOCK FEEDTHROUGH 400 kHz, MIDSCALE POWER-ON GLITCH RESET TO ZERO SCALE AVDD = 5.5 V, Clock Feedthrough Impulse ~1.5 nV-s Internal Reference Enabled AVDD = 5.
PAGE 15
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted DAC OUTPUT NOISE DENSITY vs FREQUENCY INTERNAL REFERENCE ENABLED DAC OUTPUT NOISE DENSITY vs FREQUENCY INTERNAL REFERENCE DISABLED 800 300 AVDD = 5.5 V, DAC Output Unloaded, Internal Reference = 2.
PAGE 16
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER SUPPLY CURRENT vs TEMPERATURE POWER SUPPLY CURRENT vs DIGITAL INPUT CODE 1.30 1.30 1.20 1.10 Power Supply Current - mA Power Supply Current - mA 1.20 AVDD = 3.6 V, External Reference = 3.3 V 1.10 1.00 0.90 0.80 1.00 0.90 0.80 0.70 0.60 0.50 0.
PAGE 17
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) 1.00 0.25 AVDD = 2.7 V, External Reference = 2.5 V 0.80 0.15 0.60 0.10 DNL - Error - LSB INL - Error - LSB 0.40 0.20 0.00 -0.20 0.
PAGE 18
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+125°C) 1.00 0.25 AVDD = 2.7 V, 0.80 External Reference = 2.5 V 0.20 0.60 0.15 0.40 0.10 DNL - Error - LSB INL - Error - LSB LINEARITY ERROR vs DIGITAL INPUT CODE (+125°C) 0.20 0.00 -0.
PAGE 19
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER-DOWN CURRENT vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 0.20 AVDD = 2.7 V, 4.20 External Reference = 2.5 V 3.90 3.60 AVDD = 2.7 V, External Reference = 2.5 V 0.15 0.10 Full-Scale Error - %FSR Power Supply Current - mA 4.70 4.50 3.30 3.
PAGE 20
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 2.500 0.60 AVDD = 2.7 V, External Reference = 2.5 V, DAC Loaded with FFFh 2.495 Channel B AVDD = 2.7 V, External Reference = 2.5 V, DAC Loaded with 000h 0.50 2.
PAGE 21
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted FULL-SCALE SETTLING TIME: 2.7V RISING EDGE FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE AVDD = 2.7 V, From Code FFFh to 000h External Reference = 2.5 V AVDD = 2.7 V, From Code 000h to FFFh External Reference = 2.
PAGE 22
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER-ON GLITCH RESET TO MIDSCALE POWER-OFF GLITCH AVDD = 2.7 V, External Reference = 2.5 V, DAC = Mid Scale, DACs Unloaded VOUT - 2 mV/div AVDD = 2.
PAGE 23
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) The DAC7678 architecture consists of eight string DACs each followed by an output buffer amplifier. The DAC7678 also includes an internal 2.5V reference with a maximum 25ppm/°C temperature drift performance, offering a 5V, full-scale output voltage. Figure 86 shows a principal block diagram of the DAC architecture. VREFIN/VREFOUT 150kW will be un-shorted if external reference is used.
PAGE 24
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com INTERNAL REFERENCE which consists of 8 bit Address Byte plus 24 bit serial command as shown in Table 1. During the time that the internal reference is disabled, the DAC functions normally using an external reference. However, when switching to the external reference the internal gain is dynamically switched to one. Therefore appropriate value of external reference should be used per the desired output voltage.
PAGE 25
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 Flexible Mode (see Table 3, Table 4, Table 5 and Table 6) internal reference operating mode. When performing a power cycle to reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference remains powered down until a valid write sequence is applied to power up the internal reference.
PAGE 26
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com TWO-WIRE, I2C-COMPATIBLE INTERFACE The I2C™ is a 2-wire serial interface developed by Philips Semiconductor (see I2C™-Bus Specification, Rev. 03, June 2007). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C™ compatible devices connect to the I2C™ bus through open drain I/O pins, SDA and SCL.
PAGE 27
DAC7678 www.ti.com • SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 89). This action releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices recognize the stop condition.
PAGE 28
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com Table 7. Update Sequence MSB ··· LSB MSB ··· LSB MSB ACK ··· LSB ACK MSB ··· LSB ACK ACK Address (A) Byte Command/Access Byte MSDB LSDB DB[32:24] DB[23:16] DB[15:8] DB[7:0] SPACING The CA byte sets the operational mode of the selected DAC7678.
PAGE 29
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 Command and Access (CA) Byte The Command and Access Byte, as shown in Table 11, controls which command is executed and which register is being accessed when writing to or reading from the DAC7678. See Table 12 for a list of write and read commands. Table 11. Command and Access Byte MSB C3 LSB C2 C1 Command bits C0 A3 A2 A1 Access bits A0 Table 12.
PAGE 30
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com Table 13. MSDB MSB LSB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 Most Significant Data Byte (MSDB) 2. Then send a command byte for the register to be read. The device will acknowledge this event again. 3. Then send a repeated start with the slave address and the R/W bit set to '1' for reading. The device will also acknowledge this event. 4. Then the device writes the MSDB byte of the addressed register.
PAGE 31
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 Table 17.
PAGE 32
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com Table 17.
PAGE 33
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 Table 17. Control Matrix for Write Commands (continued) COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Software Reset 0 1 1 1 X X X X 0 0 X X X X X X X X X X X X X X Software reset (default). Equivalent to power-on reset (POR).
PAGE 34
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com Table 18.
PAGE 35
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 POWER-ON RESET TO ZERO-SCALE OR MID-SCALE The DAC7678 contains a power-on reset (POR) circuit that controls the output voltage during poweron. For devices housed in the TSSOP package, at power-on, all DAC registers are filled with zeros and the output voltages of all DAC channels are set to zero-scale. For devices housed in the QFN package, all DAC registers are set to have all DAC channels power on depending of the state of the RSTSEL pin.
PAGE 36
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com When both the PD0 and PD1 bits are set to '0', the device works normally with its typical consumption of 1.49 mA at 5.5V. The reference is included with the operation of all eight channels. However, for the three power-down modes, the supply current falls to 0.42 µA at 5.5V (0.25 µA at 2.7V).
PAGE 37
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 OPERATING EXAMPLES: DAC7678 For the following examples X = don’t care; value can be either '0' or '1'.
PAGE 38
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com APPLICATION INFORMATION INTERNAL REFERENCE Where: The internal reference of the DAC7678 does not require an external load capacitor for stability because it is stable with any capacitive load. However, for improved noise performance, an external load capacitor of 100nF or larger connected to the VREFIN/VREFOUT output is recommended. Figure 94 shows the typical connections required for operation of the DAC7678 internal reference.
PAGE 39
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 Long-Term Stability Long-term stability/aging refers to the change of the output voltage of a reference over a period of months or years. This effect lessens as time progresses (see Figure 3, the typical long-term stability curve). The typical drift value for the internal reference is 100ppm from 0 hours to 2160 hours. This parameter is characterized by powering-up 19 units and measuring them at regular intervals for a period of 2160 hours.
PAGE 40
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com CONNECTING MULTIPLE DEVICES VDD Pull-Up Resistors 1kW to 10kW (typ) Microcontroller or Microprocessor 2 with I C Port SCL SDA 1 LDAC SCL 16 2 ADDR0 SDA 15 3 AVDD 4 VOUTA 5 VOUTC VOUTD 12 6 VOUTE VOUTF 11 7 VOUTG VOUTH 10 8 VREFIN/VREFOUT GND 14 DAC7678 Top View Multiple devices of DAC7678 family can be connected on the same bus.
PAGE 41
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this section summarizes selected specifications related to digital-to-analog converters. STATIC PERFORMANCE Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and provide information on the accuracy of the DAC.
PAGE 42
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com Power-Supply Rejection Ratio (PSRR) Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is measured in decibels (dB). Monotonicity Monotonicity is defined as a slope whose sign does not change.
PAGE 43
DAC7678 www.ti.com SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 analog output. As with the GND connection, AVDD should be connected to a power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a 1µF to 10µF capacitor and 0.1µF bypass capacitor are strongly recommended.
PAGE 44
DAC7678 SBAS493B – FEBRUARY 2010 – REVISED JULY 2012 www.ti.com REVISION HISTORY Changes from Original (February 2010) to Revision A • Page Changed the data sheet From: Product Preview status To : Production ............................................................................. 1 Changes from Revision A (August 2010) to Revision B Page • Changed in Table 17, Power-Down Register section, bit DB12 through bit DB5 values have been reversed ..................
PAGE 45
PACKAGE OPTION ADDENDUM www.ti.
PAGE 46
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7678SPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC7678SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 DAC7678SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
PAGE 47
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7678SPWR TSSOP PW 16 2000 367.0 367.0 35.0 DAC7678SRGER VQFN RGE 24 3000 367.0 367.0 35.0 DAC7678SRGET VQFN RGE 24 250 210.0 185.0 35.
PAGE 48
PAGE 49
PAGE 50
PAGE 51
PAGE 52
PAGE 53
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.