DAC7734 DAC 773 4 www.ti.com SBAS138A – DECEMBER 1999 – REVISED OCTOBER 2008 16-Bit, Quad Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● LOW POWER: 200mW ● UNIPOLAR OR BIPOLAR OPERATION ● SINGLE SUPPLY OUTPUT RANGE: +10V ● DUAL SUPPLY OUTPUT RANGE: ±10V ● SETTLING TIME: 10µs to 0.
SPECIFICATIONS (Dual Supply) At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, and VREFL = –10V, unless otherwise noted.
SPECIFICATIONS (Single Supply) At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = GND, VREFH = +10V, and VREFL = +50mV, unless otherwise noted.
ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VCC to VSS ........................................................................... –0.3V to +32V VCC to AGND ...................................................................... –0.3V to +16V VSS to AGND ...................................................................... +0.3V to –16V AGND to DGND ................................................................. –0.3V to +0.3V VREFH to AGND ............................................
PIN CONFIGURATION PIN DESCRIPTIONS Top View NC SSOP 1 48 VOUTA Sense PIN NAME DESCRIPTION 1 NC No Connection 2 NC No Connection 3 SDI DGND Serial Data Input NC 2 47 VOUTA 4 SDI 3 46 AGND 5 CLK 6 DGND Digital Ground 7 LDAC DAC Register Load Control, Rising Edge Triggered Digital Ground Data Clock Input DGND 4 45 VSS CLK 5 44 VREFL AB Sense 8 DGND Digital Ground DGND 6 43 VREFL AB 9 LOAD DAC Input Register Load Control, Active Low LDAC 7 42 VREFH AB 1
TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified. DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified. +85°C (cont.) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified. POSITIVE FULL-SCALE ERROR vs TEMPERATURE ZERO-SCALE ERROR vs TEMPERATURE 2 Code (FFFFH) Code (0000 (0040H) 1.5 Positive Full-Scale Error (mV) Negative Full-Scale Error (mV) 2 1 DAC A 0.5 0 DAC C –0.5 DAC B DAC D –1 –1.5 –2 0 10 20 30 40 50 60 70 80 DAC D 0.5 0 –0.5 DAC C DAC A –1 –1.
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs RLOAD POWER SUPPLY REJECTION RATIO vs FREQUENCY 0 16 –10 14 –20 12 +15V VOUT (V) PSRR (dB) –30 –40 –50 –60 +5V Source 10 8 6 4 –70 –80 2 –90 0 0.01 Sink 1k 100 10k 100k 1M 0.
TYPICAL PERFORMANCE CURVES: VSS = –15V At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. +85°C (cont.) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. REFERENCE CURRENT vs CODE All DACs Sent to Indicated Code (DAC C and D) VREFH VREFL 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH VREF (Current (mA) VREF (Current (mA) 2.5 2.0 1.5 1.0 0.5 0 –0.5 2.5 2.0 1.5 1.0 0.5 0 –0.5 VREFL 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. SUPPLY CURRENT vs CODE OUTPUT VOLTAGE vs RLOAD 7 6 5 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 15 10 Source (mA) VOUT (V) 5 0 –5 Sink –10 –15 0.01 0.
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. OUTPUT VOLTAGE MID-SCALE GLITCH PERFORMANCE Output Voltage (200mV/div) Output Voltage (200mV/div) OUTPUT VOLTAGE MID-SCALE GLITCH PERFORMANCE 7FFFH to 8000H +5V LDAC 0 +5V LDAC 0 Time (1µs/div) Time (1µs/div) DAC7734 SBAS138A 8000H to 7FFFH www.ti.
THEORY OF OPERATION The digital input is a 24-bit serial word that contains a 2-bit address code for selecting one of four DACs, a quick load bit, five unused bits, and the 16-bit DAC code (MSB first). The converters can be powered from either a single +15V supply or a dual ±15V supply and a +5V logic supply. The device offers a reset function that immediately sets all DAC output voltages and DAC registers to mid-scale code 8000H or to zero-scale, code 0000H.
Serial Data In Clock Load DAC Registers Load Chips Select Serial Data Out +5V Reset DAC Registers + +5V 1µF 1 NC VOUTA Sense 48 2 3 NC VOUTA 47 SDI AGND 46 4 DGND 5 CLK 6 –10V to +10V –15V VSS 45 VREFL AB Sense 44 DGND VREFL AB 43 –10.000V 7 LDAC VREFH AB 42 +10.
The current into the VREFH input and out of VREFL depends on the DAC output voltages, and can vary from a few microamps to approximately 2.0mA. The reference input appears as a varying load to the reference. The DAC7734 features a reference drive and sense connection such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. Figures 5 through 9 show different reference configurations, and the effect on the linearity and differential linearity.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, 25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.
DAC7734 VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUT +V 100Ω OPA350 1000pF VOUTB Sense 40 VOUTB 39 1kΩ 2200pF 0.05V 50Ω 100Ω 1000pF 99kΩ +V 2200pF OPA227 +5V VOUT NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp. FIGURE 9. Single-Supply Buffered Reference with a Reference Low of 50mV and Reference High of +5V.
DIGITAL INTERFACE Table I shows the basic control logic for the DAC7734. The interface consists of a Signal Data Clock (CLK) input, Serial Data (SDI), DAC Input Register Load Control Signal (LOAD), and DAC Register Load Control Signal (LDAC). In addition, a Chip Select (CS) input is available to enable serial communication when there are multiple serial devices.
SERIAL-DATA OUTPUT The Serial-Data Output (SDO) is the internal shift register output. For DAC7734, the SDO is a driven output and does not require an external pull-up. Any number of DAC7734s can be daisy-chained by connecting the SDO pin of one device to the SDI pin of the following device in the chain, as shown in Figure 11. DIGITAL TIMING Figure 12 and Table III provide detailed timing for the digital interface of the DAC7734.
(LSB) (MSB) SDI A0 A1 QUICK LOAD XXXXX D15 D14 D3 D13 D1 D2 D0 CLK tcss tCSH tLD1 tLD2 CS tLDDD LOAD tLDRW LDAC tDS tDH SDI tSDO tCL tCH CLK SDO tLDDL tLDDH LDAC tS tS ±0.003% ERROR BAND VOUT tRSTL ±0.003% ERROR BAND tRSTH RESET tRSSH tRSSS RESETSEL FIGURE 12. Digital Input and Output Timing.
Figure 13 shows a DAC7734 in a 4mA to 20mA current output configuration. The output current can be determined by Equation 3: (3) 5V – 1V N 1V • I OUT = + 250Ω 65, 536 250Ω At full-scale, the output current is 16mA, plus the 4mA, for the zero current. At zero scale, the output current is the offset current of 4mA (1V/250Ω).
Revision History DATE REVISION 10/08 A PAGE SECTION 1 — 23 Table III DESCRIPTION Updated front page format to current standard; some page layout changed. Changed symbol from "tLDDWL" to "tLDDL" (typo). NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DAC7734 SBAS138A www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7734E/1K SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 DAC7734EC/1K SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7734E/1K SSOP DL 48 1000 367.0 367.0 55.0 DAC7734EC/1K SSOP DL 48 1000 367.0 367.0 55.
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