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DAC811

Microprocessor-Compatible

12-BIT DIGITAL-TO-ANALOG CONVERTER

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

For most current data sheet and other product

information, visit www.burr-brown.com

BPO

OUT

D/A Latch

Input Latch

4 MSBs

Input Latch Input Latch

4 LSBs

12-Bit D/A Converter

Voltage Reference

10V

BPO

DESCRIPTION

The DAC811 is a complete, single-chip integrated-

circuit, microprocessor-compatible, 12-bit digital-to-

analog converter. The chip combines a precision volt-

age reference, microcomputer interface logic, and

double-buffered latch, in a 12-bit D/A converter with

a voltage output amplifier. Fast current switches and a

laser-trimmed thin-film resistor network provide a

highly accurate and fast D/A converter.

Microcomputer interfacing is facilitated by a double-

buffered latch. The input latch is divided into three

4-bit nibbles to permit interfacing to 4-, 8-, 12-, or

16-bit buses and to handle right-or left-justified data.

The 12-bit data in the input latches is transferred to the

D/A latch to hold the output value.

Input gating logic is designed so that loading the last

nibble or byte of data can be accomplished simulta-

neously with the transfer of data (previously stored in

adjacent latches) from adjacent input latches to the

D/A latch. This feature avoids spurious analog output

values while using an interface technique that saves

computer instructions.

The DAC811 is laser trimmed at the wafer level and

is specified to ±1/4LSB maximum linearity error (B

and K grades) at 25°C and ±1/2LSB maximum over

the temperature range. All grades are guaranteed mono-

tonic over the specification temperature range.

The DAC811 is available in six performance grades

and three package types. DAC811J and K are speci-

fied over the temperature ranges of 0°C to +70°C;

DAC811A and B are specified over –25°C to +85°C;

DAC811J and K are packaged in a reliable 28-pin

plastic DIP or plastic SO package, while DAC811A

and B are available in a 28-pin 0.6" wide dual-inline

hermetically sealed ceramic side-brazed package (H

package).

FEATURES

● SINGLE INTEGRATED CIRCUIT CHIP

● MICROCOMPUTER INTERFACE:

Double-Buffered Latch

● VOLTAGE OUTPUT: ±10V, ±5V, +10V

● MONOTONICITY GUARANTEED OVER

TEMPERATURE

● ±1/2LSB MAXIMUM NONLINEARITY OVER

TEMPERATURE

● GUARANTEED SPECIFICATIONS AT ±12V

AND ±15V SUPPLIES

● TTL/5V CMOS-COMPATIBLE LOGIC

INPUTS

SBAS144

Summary of content (14 pages)

PAGE 1
® DAC811 For most current data sheet and other product information, visit www.burr-brown.
PAGE 2
SPECIFICATIONS At TA = +25°C. ±VCC = 12V or 15V, unless otherwise noted. DAC811AH, JP, JU PARAMETER MIN DIGITAL INPUT Resolution Codes(1) Digital Inputs Over Temperature Range(2) VIH VIL IIH, VI = +2.7V IIL, VI = +0.4V Digital Interface Timing Over Temperature Range tWP, WR Pulse Width tAW1, NX and LDAC Valid to End of WR tDW, Data Valid to End of WR tDH, Data Valid Hold Time TYP MAX +15 +0.8 +10 ±20 ±10 ±5 ±5 ±1/2 Guaranteed ✻ ✻ ±1/2 ±3/4 ±0.2 ±0.
PAGE 3
PIN DESCRIPTIONS PIN ABSOLUTE MAXIMUM RATINGS NAME FUNCTION 1 +VDD Logic supply, +5V. 2 WR Write, command signal to load latches. Logic low loads latches. 3 LDAC Load D/A converter, enables WR to load the D/A latch. Logic low enables. 4 NA Nibble A, enables WR to load input latch A (the most significant nibble). Logic low enables. 5 NB Nibble B, enables WR to load input latch B. Logic low enables. 6 NC Nibble C, enables WR to load input latch C (the least significant nibble).
PAGE 4
TIMING DIAGRAMS Write Cycle #2 Load second rank from first rank: NA , NB , N C = 1 Write Cycle #1 Load first rank from Data Bus: LDAC = 1 tAW tAW LDAC N A , NB , N C tWP tDW WR DB11 –DB0 tSET tWP tDH WR ±1/2LSB DISCUSSION OF SPECIFICATIONS DRIFT Gain drift is a measure of the change in the full scale range (FSR) output over the specification temperature range. Drift is expressed in parts per million per degree centigrade (ppm/°C).
PAGE 5
The D/A latch is controlled by LDAC and WR. LDAC and WR are internally NORed so that the latches transmit data to the D/A switches when both LDAC and WR are at logic 0. When either LDAC or WR are at logic 1, the data is latched in the D/A latch and held until LDAC and WR go to logic 0. Percent of FSR per Percent of Change of Power Supply Voltage 1 –VCC 0.1 V DD 0.01 All latches are level-triggered. Data present when the control signals are logic 0 will enter the latch.
PAGE 6
±12V OPERATION + Full Scale The DAC811 is fully specified for operation on ±12V power supplies. However, in order for the output to swing to ±10V, the power supplies must be ±13.5V or greater. When operating with ±12VB supplies, the output swing should be restricted to ±8V in order to meet specifications. Range of Gain Adjust Full Scale Range Analog Output 1LSB Range of Offset Adj.
PAGE 7
DAC811 features separate digital and analog power supply returns to permit optimum connections for low noise and high speed performance. The analog common (pin 23) and digital common (pin 15) should be connected together at one point. Separate returns minimize current flow in low level signal paths if properly connected. Logic return currents are not added into the analog signal return path. A ±0.5V difference between ACOM and DCOM is permitted for specified operation.
PAGE 8
-BIT INTERFACE The control logic of DAC811 permits interfacing to rightjustified data formats, as illustrated in Figure 9. When a 12-bit D/A converter is loaded from an 8-bit bus, two bytes of data are required. Figures 10 and 11 show an addressing scheme for right-justified and left-justified data respectively. The base address is decoded from the high-order address bits. A0 and A1 address the appropriate latches. Note that adjacent addresses are used.
PAGE 9
INTERFACING MULTIPLE DAC811s IN 8-BIT SYSTEMS Many applications, such as automatic test systems, require that the outputs of several D/A converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set of eight adjacent addresses, to load the input latches of four DAC811s. The example shows a right-justified data format. eight address spaces for other uses.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2009 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC811JU/1K Package Package Pins Type Drawing SOIC DW 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 11.35 18.67 3.1 16.0 32.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC811JU/1K SOIC DW 28 1000 346.0 346.0 49.
PAGE 14
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.