Datasheet

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DAC8228

ControlLogic

An ogal Monit ro

ToDAC-0,DAC-1,

DAC-2,DAC-3

ToDAC-0,DAC-1,

DAC-2,DAC-3

ToDAC-4,DAC-5,DAC-6,DAC-7

DAC8228

OFFSET-B

AGND-B

OUT

-7

MON

OFFSET-A

AGND-A

REF-B

Reference

BufferB

InternalTrimming

Zero/Gain;INL

Reference

BufferA

OFFSET

DACA

OFFSET

DACB

DAC-0

Latch-0

Power-Up/

Power-Down

Control

(SameFunctionBlocks

forAllChannels)

REF-A

LDAC

RST

RSTSEL

LDAC

CLR

USB/BTC

BUSY

GPIO

D13

R/W

ParallelBusInterface

IOV

DGND DV

V -0

OUT

V -7

OUT

RefBufferA

RefBufferB

OFFSET-B

Mux

Command

Registers

InputData

Correction

Engine

(WhenCorrectionEngineDisabled)

DAC-0

Data

UserCalibration:

ZeroRegister0

GainRegsiter0

V -0

OUT

DAC8228

www.ti.com

SBAS462A –JUNE 2009–REVISED NOVEMBER 2009

Octal, 14-Bit, Low-Power, High-Voltage Output, Parallel Input

DIGITAL-TO-ANALOG CONVERTER

Check for Samples: DAC8228

FEATURES

DESCRIPTION

• Bipolar Output: ±3V, up to ±16.5V

The DAC8228 is a low-power, octal, 14-bit

digital-to-analog converter (DAC). With a 5V

• Unipolar Output: 0V to +33V

reference, the output can either be a bipolar ±15V

• 14-Bit Resolution

voltage when operating from a dual ±15.5V (or

• Low Power: 13.5mW/Ch

higher) power supply, or a unipolar 0V to +30V

• Relative Accuracy: 1LSB Max voltage when operating from a +30.5V power supply.

With a 5.5V reference, the output can be ±16.5V for a

• Flexible User Calibration

dual ±17V (or higher) power supply, or a unipolar 0V

• Low Zero/Full-Scale Error

to +33V voltage when operating from a +33.5V (or

– Before User Calibration: ±2.5 LSB Max

higher) power supply. This DAC provides low-power

operation, good linearity, and low glitch over the

– After User Calibration: ±1 LSB

specified temperature range of –40°C to +105°C. This

• Low Glitch: 4nV-s

device is trimmed in manufacturing and has very low

• Settling Time: 15μs

zero and full-scale error. In addition, user calibration

can be performed to achieve ±1 LSB bipolar

• Channel Monitor Output

zero/full-scale error for a bipolar supply, or ±1 LSB

• Programmable Gain: x4, x6

zero-code/full-scale error for a unipolar supply over

• Programmable Offset

the entire signal chain. The output range can be

offset by using the DAC Offset Register.

• 14-Bit Parallel Interface:

50MHz (Write Operation)

The DAC8228 features a standard, high-speed, 14-bit

• Packages: QFN-56 (8mm x 8mm),

parallel interface that operates at up to 50MHz and is

1.8V, 3V, and 5V logic compatible, to communicate

TQFP-64 (10mm x 10mm)

with a DSP or microprocessor. The eight DACs and

the auxiliary registers are addressed with five address

APPLICATIONS

lines. The device features double-buffered interface

• Automatic Test Equipment

logic. An asynchronous load input (LDAC) transfers

• PLC and Industrial Process Control

data from the DAC data register to the DAC latch.

• Communications

The asynchronous CLR input sets the output of all

eight DACs to AGND. The V

MON

pin is a monitor

output that connects to the individual analog outputs,

the offset DAC, and the reference buffer outputs

through a multiplexer (mux).

The DAC8228 is pin-to-pin compatible with the

DAC8728 (16-bit) and the DAC7728 (12-bit).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (54 pages)

PAGE 1
DA C8 228 DAC8228 DA C8 228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 Octal, 14-Bit, Low-Power, High-Voltage Output, Parallel Input DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC8228 FEATURES DESCRIPTION • • • • • • • The DAC8228 is a low-power, octal, 14-bit digital-to-analog converter (DAC). With a 5V reference, the output can either be a bipolar ±15V voltage when operating from a dual ±15.
PAGE 2
DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
PAGE 4
DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8228 PARAMETER CONDITIONS MIN TYP MAX UNIT V ANALOG OUTPUT (VOUT-0 to VOUT-7) (3) Voltage output (4) Output impedance VREF = +5V –15 +15 VREF = +1.5V –4.
PAGE 5
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
PAGE 6
DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8228 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD +4.5 +18 V AVSS –18 –4.5 V DVDD +2.7 +5.5 V IOVDD +1.
PAGE 7
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS: Single-Supply All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
PAGE 8
DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Single-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
PAGE 9
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS: Single-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted. DAC8228 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD +9 +36 V DVDD +2.7 +5.5 V IOVDD +1.7 DVDD AIDD DIDD IOIDD Power dissipation 4.
PAGE 10
DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.
PAGE 11
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 PIN DESCRIPTIONS (continued) PIN NAME (2) PIN NO. QFN-56 TQFP-64 I/O DESCRIPTION LDAC 17 18 I Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the contents of the DAC Data Register are transferred to it. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated. See the DAC Output Update section for details.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TIMING DIAGRAMS t8 t1 CS t9 CS t10 t2 t3 R/W R/W t12 t11 t13 D13:D0 t5 t4 A4:A0 A4:A0 t14 Hi-Z Hi-Z Hi-Z D13:D0 Hi-Z t6 Figure 2. Read Operation t7 Write Operation 1: 1. Writing to the Configuration Register, Offset Register, Monitor Register, GPIO Register. 2. Writing to the DAC Input Registers, Zero Registers, and Gain Registers in Asynchronous mode (LDAC pin is tied low). Figure 3.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TIMING CHARACTERISTICS (1) (2) (3) (4) (5) At –40°C to +105°C, DVDD = +5V to +5.5V, and IOVDD = +5V, unless otherwise noted.
PAGE 14
DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TIMING CHARACTERISTICS (1) www.ti.com (2) (3) (4) (5) At –40°C to +105°C, DVDD = +3V to +5V, and IOVDD = +3V, unless otherwise noted.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TIMING CHARACTERISTICS (1) (2) (3) (4) (5) At –40°C to +105°C, DVDD = +3V to +5V, and IOVDD = +1.8V, unless otherwise noted.
PAGE 16
DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Dual-Supply At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.00 1.00 TA = +25°C 0.75 0.50 DNL Error (LSB) INL Error (LSB) 0.50 0.25 0 -0.25 DAC0 DAC1 DAC2 DAC3 -0.50 -0.75 -1.00 0 2048 4096 DAC4 DAC5 DAC6 DAC7 0.25 0 -0.25 DAC0 DAC1 DAC2 DAC3 -0.50 -0.75 -1.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.00 1.00 TA = -40°C 0.75 0.50 DNL Error (LSB) INL Error (LSB) 0.50 0.25 0 -0.25 0 -0.25 -0.50 -0.75 -0.75 -1.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE 1.00 1.00 0.75 0.75 0.50 0.50 INL Max DNL Error (LSB) INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 0.25 0 -0.25 INL Min -0.50 0.25 DNL Max 0 DNL Min -0.25 -0.50 -0.75 -0.75 -1.00 -1.
PAGE 19
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. GAIN ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE 5 5 LSB = 1.
PAGE 20
DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. BIPOLAR ZERO ERROR vs AVDD AND AVSS GAIN ERROR vs AVDD AND AVSS 5 5 VREF = 2.048V Gain = 4 3 3 2 2 1 0 -1 -2 DAC0 DAC1 DAC2 DAC3 -3 -4 1 0 -1 -2 DAC4 DAC5 DAC6 DAC7 DAC0 DAC1 DAC2 DAC3 -3 -4 -5 6 8 10 12 AVDD = -AVSS (V) 14 16 18 4 6 8 10 12 AVDD = -AVSS (V) Figure 29.
PAGE 21
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
PAGE 22
DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
PAGE 23
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Dual-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted. IOVDD SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 3.0 2000 Code = 2000h 1800 IOVDD Supply Current (mA) Output Voltage Noise Density (nV/ÖHz) OUTPUT NOISE SPECTRAL DENSITY vs FREQUENCY 1600 1400 1200 Gain = 6 1000 800 Gain = 4 600 400 IOVDD Values are Shown for Logic Level Change on D0 to D13.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Single-Supply At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.00 1.00 TA = +25°C 0.75 0.50 DNL Error (LSB) INL Error (LSB) 0.50 0.25 0 -0.25 DAC0 DAC1 DAC2 DAC3 -0.50 -0.75 -1.00 0 2048 4096 DAC4 DAC5 DAC6 DAC7 0.25 0 -0.25 DAC0 DAC1 DAC2 DAC3 -0.50 -0.75 -1.
PAGE 25
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.00 1.00 TA = -40°C 0.75 0.50 DNL Error (LSB) INL Error (LSB) 0.50 0.25 0 -0.25 0 -0.25 -0.50 -0.75 -0.75 -1.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1.00 1.00 0.75 0.75 0.50 0.50 DNL Error (LSB) INL Error (LSB) LINEARITY ERROR vs TEMPERATURE INL Max 0.25 0 -0.25 INL Min -0.50 0.25 DNL Max 0 DNL Min -0.25 -0.50 -0.75 -0.75 -1.00 -1.
PAGE 27
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. GAIN ERROR vs TEMPERATURE 5 DAC0 DAC1 DAC2 DAC3 LSB = 1.83mV 4 3 2 5 DAC4 DAC5 DAC6 DAC7 3 1 0 -1 -2 2 1 0 -1 -2 -3 -3 -4 -4 -5 DAC0 DAC1 DAC2 DAC3 -5 -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 125 -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 Figure 69.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. ZERO-SCALE ERROR vs AVDD GAIN ERROR vs AVDD 5 5 VREF = 2.048V Code = 0040h Gain = 4 3 3 2 1 0 -1 -2 DAC0 DAC1 DAC2 DAC3 -3 -4 2 1 0 -1 -2 DAC4 DAC5 DAC6 DAC7 DAC0 DAC1 DAC2 DAC3 -3 -4 -5 12 16 20 24 AVDD (V) 28 32 36 8 12 16 20 24 AVDD (V) Figure 75.
PAGE 29
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs DIGITAL INPUT CODE 8 8 7 7 6 6 5 5 IAVDD (mA) IAVDD (mA) Code = 2000h 4 3 4 3 2 2 1 1 0 0 -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 0 125 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 80. Figure 81.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS: Single-Supply (continued) At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted. OUTPUT VOLTAGE vs SINK CURRENT CAPABILITY OUTPUT VOLTAGE vs SOURCE CURRENT CAPABILITY 2.5 30.5 2.0 30.0 3FFFh 3F80h 29.5 1.5 0200h 0100h 0080h VOUT (V) VOUT (V) 3FC0h 1.0 3F00h 29.0 3E00h 28.5 0.5 28.0 0 Operation Near AGND Rail Operation Near AVDD Rail 0040h 0000h 27.5 -0.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com THEORY OF OPERATION GENERAL DESCRIPTION The DAC8228 contains eight DAC channels and eight output amplifiers in a single package. Each channel consists of a resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, each with a value of R, from REF to AGND, as shown in Figure 95. This type of architecture provides DAC monotonicity.
PAGE 33
DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 USER-CALIBRATION FOR ZERO ERROR AND GAIN ERROR The DAC8228 implements a digital user-calibration function that allows for trimming gain and zero errors on the entire signal chain. This function can eliminate the need for external adjustment circuits. Each DAC channel has a Zero Register and Gain Register.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com If the user-calibration function is not needed, the correction engine can be turned off to speed up the device. Setting the SCE bit in the Configuration Register to '0' turns off the correction engine. Setting SCE to '1' enables the correction engine. When SCE = '0' (default), the data are directly transferred to the DAC Data Register.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 INPUT DATA FORMAT The USB/BTC pin defines the input data format and the Offset DAC format. When this pin connects to DGND, the Input DAC data and Offset DAC data are straight binary, as shown in Table 2 and Table 4. When this pin is connected to IOVDD, the Input DAC data and Offset DAC data are twos complement, as shown in Table 3 and Table 5. Table 2.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com OFFSET DACS There are two 14-bit Offset DACs: one for Group A, and one for Group B. The Offset DACs allow the entire output curve of the associated DAC groups to be shifted by introducing a programmable offset. This offset allows for asymmetric bipolar operation of the DACs or unipolar operation with bipolar supplies.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 VOUT = GAIN x V1 - (GAIN - 1) x VOFF DAC Channel V1 VOUT AGND-x Offset DAC VOFF OFFSET Figure 96. Output Amplifier and Offset DAC OUTPUT AMPLIFIERS The output amplifiers can swing to 0.5V below the positive supply and 0.5V above the negative supply. This condition limits how much the output can be offset for a given reference voltage. The maximum range of the output for ±17V power and a +5.5V reference is –16.5V to +16.5V for gain = 6.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com GENERAL-PURPOSE INPUT/OUTPUT PIN (GPIO) The GPIO pin is a general-purpose, bidirectional, digital input/output, as shown in Figure 97. When the GPIO pin acts as an output, the pin status is determined by the corresponding GPIO bit in the GPIO Register. The pin output is high-impedance when the GPIO bit is set to '1', and is logic low when the GPIO bit is cleared to '0'.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 POWER-ON RESET The DAC8228 contains a power-on reset circuit that controls the output during power-on and power down. This feature is useful in applications where the known state of the DAC output during power-on is important. The Offset DAC Registers, DAC Data Registers, and DAC latches are loaded with the value defined by the RSTSEL pin, as shown in Table 8. The Gain Registers and Zero Registers are loaded with default values.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com UPDATING THE DAC OUTPUTS Depending on the status of both CS and LDAC, and after data have been transferred into the DAC Data registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode. This update mode is established at power-on. If asynchronous mode is desired, the LDAC pin must be permanently tied low before power is applied to the device.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 MONITOR OUTPUT PIN (VMON) The VMON pin is the channel monitor output. It monitors either of the DAC outputs, offset DAC outputs, or reference buffer outputs. The channel monitor function consists of an analog multiplexer addressed via the parallel interface, allowing any channel output, reference buffer output, or offset DAC output to be routed to the VMON pin for monitoring using an external ADC.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com PARALLEL INTERFACE The DAC8228 interfaces with microprocessors using a 14-bit data bus. The interface is double-buffered, allowing simultaneous updating of all DACs. Each DAC has an input data register, DAC data register, user-calibration zero register, user-calibration gain register, and DAC latch.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 INTERNAL REGISTERS The DAC8228 internal registers consist of the Configuration Register, the Monitor Register, the DAC Input Data Registers, the Zero Registers, the Gain Registers, the DAC Data Registers, and the Busy Flag Register, and are described in the following section. The Configuration Register specifies which actions are performed by the device. Table 11 shows the details. Table 11.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com Monitor Register (default = 0000h). The Monitor Register selects one of the DAC outputs, reference buffer outputs, or offset DAC outputs to be monitored through the VMON pin. Only one bit at a time can be set to '1'. When bits [D13:D2] = '0', the monitor is disabled and VMON is in a Hi-Z state.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 Zero Register n (where n = 0 to 7). Default = 0000h. The Zero Register stores the user-calibration data that are used to eliminate the offset error, as shown in Table 14. The data are 14 bits wide, 1 LSB/step, and the total adjustment is –8192 LSB to +8191 LSB, or ±50% of full-scale range. The Zero Register uses a twos complement data format. Table 14.
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DAC8228 SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com GPIO Register. Default = 2000h. The GPIO Register determines the status of the GPIO pin. D13 D12 GPIO (1) X (1) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X = don't care. Writing to this bit has no effect; reading the bit returns '0'. GPIO For write operations, the GPIO pin operates as an output.
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DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 APPLICATION INFORMATION PRECISION VOLTAGE REFERENCE SELECTION To achieve the optimum performance from the DAC8228 over the full operating temperature range, a precision voltage reference must be used. Careful consideration should be given to the selection of a precision voltage reference. The DAC8228 has two reference inputs, REF-A and REF-B.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8228SPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 DAC8228SRTQR QFN RTQ 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 DAC8228SRTQT QFN RTQ 56 250 330.0 16.4 8.3 8.3 2.25 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8228SPAGR TQFP PAG 64 1500 367.0 367.0 45.0 DAC8228SRTQR QFN RTQ 56 2000 336.6 336.6 28.6 DAC8228SRTQT QFN RTQ 56 250 336.6 336.6 28.
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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.