Datasheet

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DAC8234

FEATURES DESCRIPTION

APPLICATIONS

Power-Down

ControlLogic

SCLK

SDI

SDO

IOV

RST

UNI/BIP-A

UNI/BIP-B

LDAC

GPIO-0

GPIO-1

AIN

DAC8234

ReferenceBufferA

MON

R -0

FB1

R -0

FB2

V -0

OUT

SGND-0

14-BitDAC

SPI

Shift

Input

Control

Logic

Control

Logic

DGND DV

DACRegister0

ZeroRegister0

GainRegister0

AGND AV

REF-A REFGND-A

Analog

Monitor

ReferenceBufferB

REF-B REFGND-B

R -1

FB1

R -1

FB2

V -1

OUT

SGND-1

14-BitDAC

DACRegister1

ZeroRegister1

GainRegister1

R -2

FB1

R -2

FB2

V -2

OUT

SGND-2

14-BitDAC

DACRegister2

ZeroRegister2

GainRegister2

R -3

FB1

R -3

FB2

V -3

OUT

SGND-3

14-BitDAC

DACRegister3

ZeroRegister3

GainRegister3

CommandRegister

DAC8234

www.ti.com

........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009

Quad, 14-Bit, High-Accuracy, ± 16V Output, Serial Input

DIGITAL-TO-ANALOG CONVERTER

2345

• Bipolar Output: Up to ± 16V

The DAC8234 is a high-accuracy, quad-channel,

14-bit digital-to-analog converter (DAC) that operates

• Unipolar Output: 0V to +20V

from supply voltages of ± 5V to ± 18V in bipolar output

• 14-Bit Monotonic

mode, and from ± 5V to +24V/ – 12V in unipolar mode.

• Relative Accuracy: 0.5 LSB Max

With a 5V reference, the DAC8234 can be configured

• Low Zero and Gain Errors to output ± 10V, ± 5V, 0V to 20V, or 0V to 10V. The

DAC8234 provides 14-bit monotonicity, excellent

– Before User Calibration: 1 LSB

integral nonlinearity (INL) error of ± 0.5 LSB, low

– After User Calibration:

glitch, and low noise over the operating temperature

0.031 LSB Zero Error, 0.25 LSB Gain Error

range of – 40 ° C to +105 ° C. This device is trimmed in

production for very low zero and gain errors. In

• Low Noise: 60nV/ √ Hz

addition, the DAC8234 implements a

• Settling Time: 6 µ s

user-programmable system-level calibration function

• Configurable Gain: x2/x4

to achieve ± 0.031 LSB zero error and ± 0.25 LSB gain

• Analog Output Monitor

error.

• Power-Down Mode

The DAC8234 has integrated reference buffers and

output buffers. It features a standard high-speed

• SPI™: Up to 50MHz, 1.8V/3V/5V Logic

1.8V, 3V, or 5V serial peripheral interface (SPI) that

• Daisy-Chain Mode

operates at clock rates of up to 50MHz to

• Operating Temperature: – 40 ° C to +105 ° C

communicate with a DSP or microprocessor. The four

• Packages: QFN-40 (6x6mm), TQFP-48 (7x7mm)

DAC channels and the auxiliary registers are

addressed with four address bits. The device features

double-buffered interface logic for simultaneous

updates of all DACs. An asynchronous load input

• Automatic Test Equipment

( LDAC) transfers data from the input data register to

• Instrumentation

the DAC latch, and the contents of the DAC latch set

• Industrial Process Control

the output voltage. The asynchronous RST input sets

• Communications the output of all four DACs to 0V. The V

MON

pin is an

analog monitor output that multiplexes the individual

DAC outputs or the AIN pin.

The DAC8234 is pin-compatible with the DAC8734

(16-bit) and the DAC7716 (12-bit).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 DSP is a trademark of Texas Instruments.

3 SPI, QSPI are trademarks of Motorola Inc.

4 Microwire is a trademark of National Semiconductor.

5 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (41 pages)

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DA C8 234 DAC8234 DA C8 234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 Quad, 14-Bit, High-Accuracy, ±16V Output, Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION 1 • • • • • 2345 • • • • • • • • • Bipolar Output: Up to ±16V Unipolar Output: 0V to +20V 14-Bit Monotonic Relative Accuracy: 0.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS All specifications at TA = TMIN to TMAX, AVDD = +11V to +18V, AVSS = –11V to –18V, VREF = REF-A = REF-B = +5V, DVDD = +5V, IOVDD = +1.8V to DVDD, AGND = DGND = REFGND-A = REFGND-B = SGND-x = 0V, and DAC gain = 4, unless otherwise noted.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = TMIN to TMAX, AVDD = +11V to +18V, AVSS = –11V to –18V, VREF = REF-A = REF-B = +5V, DVDD = +5V, IOVDD = +1.8V to DVDD, AGND = DGND = REFGND-A = REFGND-B = SGND-x = 0V, and DAC gain = 4, unless otherwise noted.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = TMIN to TMAX, AVDD = +11V to +18V, AVSS = –11V to –18V, VREF = REF-A = REF-B = +5V, DVDD = +5V, IOVDD = +1.8V to DVDD, AGND = DGND = REFGND-A = REFGND-B = SGND-x = 0V, and DAC gain = 4, unless otherwise noted.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.
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DAC8234 www.ti.com ...........................................................................................................................................
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com PIN DESCRIPTIONS (continued) PIN NAME QFN-40 TQFP-48 I/O RFB2-0 (1) 14 16 O DAC-0 RFB2 feedback RFB1-0 (1) 15 17 O DAC-0 RFB1 feedback SGND-0 16 18 I DAC-0 signal ground. Connected to REFGND-A. SGND-1 17 20 I DAC-1 signal ground. Connected to REFGND-A.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 TIMING DIAGRAMS Case 1: Stand-alone mode, LDAC tied low. t8 t4 CS t1 SCLK Input Data Register and DAC Latch Updated(1) tF t5 LDAC tR t3 t2 t6 BIT 23 (MSB) SDI t7 BIT 22 BIT 1 BIT 0 Low Case 2: Stand-alone mode, LDAC active high.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com Case 3: Daisy-Chain mode, LDAC tied low. t8 t4 CS t1 SCLK tR t3 t2 t6 BIT 23 (N) BIT 22 (N) BIT 0 (N) BIT 23 (N+1) t11 BIT 0 (N+1) t12 BIT 23 (N) SDO LDAC Input Data Register and DAC Latch Updated(1) tF t5 SDI t7 BIT 0 (N) Low Case 4: Daisy-Chain mode, LDAC active.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 Case 5: Readback for Stand-alone mode.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0 -0.1 TA = +25°C Gain = 4 VREF = 5V AVDD = +15V AVSS = -15V -0.2 -0.4 -0.5 2048 4096 0.1 0 -0.1 -0.4 -0.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR vs DIGITAL INPUT CODE (All Channels, Bipolar Operation) 0.5 Channel 0 Channel 1 Channel 2 Channel 3 0.4 INL Error (LSB) 0.3 0.2 0.1 0 -0.1 TA = +25°C Gain = 4 VREF = 5V AVDD = +15V AVSS = -15V -0.2 -0.3 -0.4 -0.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR vs TEMPERATURE (Bipolar Operation) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE (Bipolar Operation) 0.3 0.3 0.2 0 INL Min -0.1 Gain = 4 VREF = 5V AVDD = +15V AVSS = -15V -0.2 -0.3 5 -40 -25 -10 INL Error (LSB) DNL Error (LSB) INL Max 0.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) 0.5 1.5 0.4 Bipolar Zero Error (mV) 2.0 1.0 0.5 0 -0.5 TA = +25°C Gain = 4 AVDD = +18V AVSS = -18V -1.0 -1.5 -2.0 1 Bipolar Gain Error (mV) BIPOLAR ZERO ERROR vs REFERENCE VOLTAGE (10 Units, 40 Channels Total) 2 3 4 5 6 Reference Voltage (V) 7 0.2 0.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) 0.1Hz TO 10Hz NOISE (Bipolar Operation) IOVDD SUPPLY CURRENT vs LOGIC INPUT VOLTAGE IOVDD Supply Current (mA) Noise (2mV/div) 1.2 TA = +25°C Gain = 4 VREF = 0V AVDD = +15V AVSS = -15V Midscale Code TA = +25°C AVDD = +15V AVSS = -15V 1.0 IOVDD = 5V 0.8 0.6 0.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 THEORY OF OPERATION DAC ARCHITECTURE The DAC8234 is a highly-integrated, quad-channel, 14-bit, voltage-output DAC with internal reference buffers and output buffers.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 UPDATING THE DAC OUTPUTS The DAC8234 has a double-buffered interface that consists of two register banks for every channel: the input register and the DAC latch. The digital code is transferred from the SPI shift register to the addressed channel input register upon completion of a valid write sequence.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com ANALOG OUTPUT MONITOR PIN (VMON) The VMON pin is the analog output monitor. The analog output monitor function consists of an analog multiplexer addressed via the serial interface, allowing one of the four channel outputs or the AIN input to be routed to this pin for monitoring.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 SERIAL INTERFACE The DAC8234 is controlled over a versatile, three-wire serial interface that operates at clock rates of up to 50MHz and is compatible with SPI, QSPI™, Microwire™, and DSP™ standards. SPI Shift Register The SPI Shift Register is 24 bits wide.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com Read-Back Operation The READ command is used to start read-back operation. However, before read-back operation can be initiated, the SDO pin must be enabled by clearing the DSDO bit in the Command Register (DSDO = '0'); this bit is cleared by default.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 SPI SHIFT REGISTER The SPI Shift Register is 24 bits wide, as shown in Table 2. By default, the SPI shift register resets to 000000h at power-on or after a reset. Table 2.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com INTERNAL REGISTERS The DAC8234 internal registers consist of the Command Register, the Monitor Register, the DAC Input Data Registers, the Zero Registers, and the Gain Registers. Command Register. Default = 033Ch. The Command Register determines the actions performed by the DAC8234. Table 4.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 Monitor Register. Default = 0000h. The Monitor Register selects one of the four DAC outputs or the external signal AIN that is to be monitored through the VMON pin. Only one bit can be set to '1' at a time. When all bits = '0', the monitor is disabled and VMON is placed in a high-impedance state.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com Zero Register n (where n = 0, 1, 2, or 3). Default = 0000h. The Zero Register stores the user-calibration data that are used to eliminate the offset error. The data are nine bits wide, 0.03125 LSB/step, and the total adjustment is typically –8 LSB to +7.96875 LSB, or ±0.0488% of full-scale range.
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DAC8234 www.ti.com ...........................................................................................................................................
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com USER ZERO- AND GAIN-CALIBRATION The DAC8234 is trimmed during production for nominal operating conditions to have very low gain error and offset error.
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DAC8234 www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 System Zero Adjust Example The DAC8234 zero calibration feature can minimize system offset errors to 0.00019% FSR or 38µV over a 20V output range. The total adjustment range is approximately ±0.0488% of FSR, or ±9.7mV over a 20V output span.
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DAC8234 SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com LAYOUT AND GROUNDING Precision analog circuits require careful layout, adequate bypass capacitors, and a clean, well-regulated power supply to obtain the best possible dc and ac performance. A careful consideration of the power-supply and ground-return layout helps to ensure the rated performance.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8234SPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 DAC8234SRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 DAC8234SRHAT VQFN RHA 40 250 330.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8234SPFBR TQFP PFB 48 1000 367.0 367.0 38.0 DAC8234SRHAR VQFN RHA 40 2500 336.6 336.6 28.6 DAC8234SRHAT VQFN RHA 40 250 336.6 336.6 28.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.