Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 16

Quad Channel, Low Power, 16-Bit, Serial Input

DIGITAL-TO-ANALOG CONVERTER

APPLICATIONS

● PORTABLE INSTRUMENTATION

● CLOSED-LOOP SERVO-CONTROL

● PROCESS CONTROL

● DATA ACQUISITION SYSTEMS

● PROGRAMMABLE ATTENUATION

● PC PERIPHERALS

DESCRIPTION

The DAC8534 is a quad channel, 16-bit Digital-to-Analog

Converter (DAC) offering low-power operation and a flexible

serial host interface. Each on-chip precision output amplifier

allows rail-to-rail output swing to be achieved over the supply

range of 2.7V to 5.5V. The device supports a standard 3-wire

serial interface capable of operating with input data clock

frequencies up to 30MHz for IOV

= 5V.

The DAC8534 requires an external reference voltage to set

the output range of each DAC channel. Also incorporated

into the device is a power-on reset circuit which ensures that

the DAC outputs power up at zero-scale and remain there

until a valid write takes place. The DAC8534 provides a per

channel power-down feature, accessed over the serial inter-

face, that reduces the current consumption to 200nA per

channel at 5V.

The low-power consumption of this device in normal opera-

tion makes it ideally suited to portable battery-operated

equipment and other low-power applications. The power

consumption is 5mW at 5V, reducing to 4µW in power-down

mode.

The DAC8534 is available in a TSSOP-16 package with a

specified operating temperature range of –40°C to +105°C.

FEATURES

● POWER SUPPLY: +2.7V to +5.5V

●

micro

POWER OPERATION: 950µA at 5V

● 16-BIT MONOTONIC OVER TEMPERATURE

● SETTLING TIME: 10µs to ±0.003% FSR

● ULTRA-LOW AC CROSSTALK: –100dB typ

● POWER-ON RESET TO ZERO-SCALE

● ON-CHIP OUTPUT BUFFER AMPLIFIER WITH

RAIL-TO-RAIL OPERATION

● DOUBLE BUFFERED INPUT ARCHITECTURE

● SIMULTANEOUS OR SEQUENTIAL OUTPUT

UPDATE AND POWER-DOWN

● 16 CHANNEL BROADCAST CAPABILITY

● SCHMITT-TRIGGERED INPUTS

● TSSOP-16 PACKAGE

DAC8534

SBAS254D – SEPTEMBER 2002 – REVISED MARCH 2004

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Buffer

Control

Data

Buffer D

DAC

DAC D

Power-Down

Control Logic

24-Bit

Serial-to-

Parallel

Shift

Resistor

Network

IOV

GND

OUT

Data

Buffer A

DAC

DAC A

REF

SYNC

SCLK

A0 A1 LDAC

ENABLE

REF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

Summary of content (24 pages)

PAGE 1
DAC8534 DAC 8534 ® SBAS254D – SEPTEMBER 2002 – REVISED MARCH 2004 Quad Channel, Low Power, 16-Bit, Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● ● ● ● ● ● ● The DAC8534 is a quad channel, 16-bit Digital-to-Analog Converter (DAC) offering low-power operation and a flexible serial host interface. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7V to 5.5V.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) AVDD to GND ........................................................................ –0.3V to +6V Digital Input Voltage to GND ............................... –0.3V to +AVDD + 0.3V VOUTA to VOUTD to GND .................................... –0.3V to + AVDD + 0.3V Operating Temperature Range ...................................... –40°C to +105°C Storage Temperature Range .........................................
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ELECTRICAL CHARACTERISTICS (Cont.) AVDD = +2.7V to +5.5V, –40°C to +105°C, unless otherwise specified. DAC8534 PARAMETER CONDITIONS REFERENCE INPUT Reference Current MIN VREF = AVDD = +5V VREF = AVDD = +3V Reference Input Range Reference Input Impedance TYP MAX UNITS 135 80 180 120 AVDD µA µA V kΩ ±1 0.8 0.6 3 µA V V V V pF 5.5 5.
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TIMING CHARACTERISTICS(1, 2) AVDD = +2.7V to +5.5V; all specifications –40°C to +105°C unless otherwise noted. DAC8534 PARAMETER DESCRIPTION CONDITIONS MIN SCLK Cycle Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 50 33 ns ns t2 SCLK HIGH Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 26 15 ns ns t3 SCLK LOW Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 22.5 13 ns ns t4 SYNC Falling Edge to SCLK Rising Edge Setup Time IOVDD = AVDD = 2.7V to 3.
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TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. 64 48 32 16 0 –16 –32 –48 –64 CHANNEL A LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE AVDD = 5V LE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.5 0.0 –0.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE CHANNEL C 64 48 32 16 0 –16 –32 –48 –64 AVDD = 2.7V LE (LSB) LE (LSB) 64 48 32 16 0 –16 –32 –48 –64 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE AVDD = 2.7V 1.0 0.5 DLE (LSB) DLE (LSB) 1.0 CHANNEL D 0.0 –0.5 0.5 0.0 –0.5 –1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –1.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted. SINK CURRENT CAPABILITY (ALL CHANNELS) 0.150 SOURCE CURRENT CAPABILITY (ALL CHANNELS) 5.00 VREF = AVDD – 10mV DAC loaded with 0000H 0.125 VREF = AVDD – 10mV DAC Loaded with FFFFH AVDD = 5V 4.95 VOUT (V) VOUT (V) 0.100 0.075 AVDD = 5V 4.90 0.050 4.85 0.025 AVDD = 2.7V 0.000 4.80 0 1 2 3 4 0 5 1 2 3 4 5 ISOURCE (mA) ISINK (mA) SUPPLY CURRENT vs DIGITAL INPUT CODE SOURCE CURRENT CAPABILITY (ALL CHANNELS) 2.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION 1750 1500 TA = 25°C, SYNC Input (All others inputs = GND) Reference Current Included 1650 AVDD = VREF = 5V Reference Current Included 1450 1000 AVDD = VREF = 5V 1350 Frequency AIDD + IOIDD (µA) 1550 1250 1150 500 1050 AVDD = VREF = 2.7V 950 850 750 1150 1120 VLOGIC (V) 1090 5.0 1060 4.5 1030 4.0 1000 3.5 970 3.0 940 2.5 910 2.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted.
PAGE 10
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted. SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 98 0 AVDD = VREF = 5V FS = 52ksps, –1dB FSR Digital Input Measurement Bandwidth = 20kHz –10 96 –20 AVDD = 5V 94 –30 THD (dB) SNR (dB) TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY 92 AVDD = 2.7V 90 –40 THD –50 –60 –70 88 AVDD = VREF –1dB FSR Digital Input, FS = 52ksps Measurement Bandwidth = 20kHz 86 –80 3rd-Harmonic –90 84 2nd-Harmonic –100 0 500 1.0k 1.5k 2.0k 2.
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THEORY OF OPERATION VREFH DAC SECTION RDIVIDER The architecture of each channel of the DAC8534 consists of a resistor-string DAC followed by an output buffer amplifier. Figure 1 shows a simplified block diagram of the DAC architecture. VREFH 50kΩ VREF 2 R R 50kΩ To Output Amplifier (2x Gain) 70kΩ DAC Register VOUT REF (+) Resistor String REF(–) VREFL R FIGURE 1. DAC8534 Architecture.
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reference to shift the incoming logic HIGH levels to AVDD. IOVDD is ensured to operate from 2.7V to 5.5V regardless of the AVDD voltage, which ensures compatibility with various logic families. Although specified down to 2.7V, IOVDD will operate at as low as 1.8V with degraded timing and temperature performance. For lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should be as close as possible to GND voltages.
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D23 D22 D21 D20 A1 A0 Load 1 Load 0 D19 D18 D17 Don’t Care DAC Sel 1 DAC Sel 0 D16 D15 D14 D13-D0 PD0 MSB MSB-1 MSB-2...LSB DESCRIPTION (Address Select) 0/1 (A0 and A1 should correspond to the package address set via pins 13 and 14.) This address selects 1 of 4 possible devices on a single SPI data bus based on each device’s address pin(s) state.
PAGE 14
Resistor String DAC Amplifier VOUTX Power-down Circuitry Resistor Network FIGURE 5. Output Stage During Power-Down (High-Impedance). OPERATION EXAMPLES Example 1: Write to Data Buffer A; Through Buffer D; Load DAC A Through DAC D Simultaneously • 1st—Write to Data Buffer A: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ...... DB1 DB0 0 0 0 0 X 0 0 0 D15 ..... D1 D0 • 2nd—Write to Data Buffer B: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ......
PAGE 15
• Write power-down command to Data Buffer B: DAC B to 1kΩ. A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 0 0 X 0 1 1 0 1 X ........ • Write power-down command to Data Buffer C: DAC C to 100kΩ. A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 0 0 X 1 0 1 1 0 X ........ • Write power-down command to Data Buffer D: DAC D to 100kΩ and Simultaneously Update all DACs.
PAGE 16
DAC8534 to TMS320 DSP INTERFACE 80C51/80L51(1) DAC8534(1) P3.3 SYNC TXD SCLK RXD DIN Figure 9 shows the connections between the DAC8534 and a TMS320 Digital Signal Processor (DSP). A Single DSP can control up to four DAC8534s without any interface logic. DAC8534 NOTE: (1) Additional pins omitted for clarity. Positive Supply AVDD FIGURE 6. DAC8534 to 80C51/80L51 Interface. 0.
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scale change on the neighboring channel is typically less than 0.5LSBs. The AC crosstalk measured (for a full-scale, 1kHz sine wave output generated at one channel, and measured at the remaining output channel) is typically under –100dB. In addition, the DAC8534 can achieve typical AC performance of 96dB SNR (Signal-to-Noise Ratio) and 65dB THD (Total Harmonic Distortion), making the DAC8534 a solid choice for applications requiring high SNR at output frequencies at or below 4kHz.
PAGE 18
The output voltage for any input code can be calculated as follows:   D   R1 + R 2  VOUT X = VREF •  – VREF •  65536   R1   R  •  2   R1   where D represents the input code in decimal (0–65535). With VREF = 5V, R1 = R2 = 10kΩ:  10 • D  VOUT X =   – 5V  65536  This is an output voltage range of ±5V with 0000H corresponding to a –5V output and FFFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, a ±2.5V output voltage range can be achieved.
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC8534IPWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8534IPWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.