Datasheet

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

SLAS353 − DECEMBER 2001

     

    

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FEATURES

Micropower Operation: 250 µA at 5 V AV

D Power-On Reset to Min-Scale

D 16-Bit Monotonic

D Settling Time: 10 µs to ±0.003% FSR

D 16-Bit Parallel Interface

D On-Chip Output Buffer Amplifier With

Rail-to-Rail Operation

D Hardware Reset to Min-Scale or Mid-Scale

D Double-Buffered Architecture

D Asynchronous LDAC Control

D Data Readback Support

D 1.8 V Compatible Digital Interface:

− DV

= 1.8 V−5.5 V

D Wide Analog Supply Range:

− AV

= 2.7 V−5.5 V

D 32-Lead 5 mm × 5 mm TQFP Package

APPLICATIONS

Process Control

D Data Acquisition Systems

D Closed-Loop Servo Control

D PC Peripherals

D Portable Instrumentation

DESCRIPTION

The DAC8541 is a low-power, single channel, 16-bit,

voltage output DAC. Its on-chip precision output

amplifier allows rail-to-rail voltage swing to be achieved

at the output. The DAC8541 utilizes a 16-bit parallel

interface and features additional powerdown function

pins as well as hardware-enabled, asynchronous DAC

updating and reset capability.

The DAC8541 requires an external reference voltage to

set the output range of the DAC. The device

incorporates a power-on-reset circuit that ensures that

the DAC output powers up at min-scale and remains

there until a valid write takes place to the device. In

addition, the DAC8541 contains a power-down feature,

accessed via two hardware pins, that when enabled

reduces the current consumption of the device to

200 nA at 5 V.

The low power consumption of this device in normal

operation makes it ideally suited for use in portable

battery operated equipment applications. The power

consumption is 1.2 mW at AV

= 5 V reducing to 1 µW

in power-down mode.

The DAC8541 is available in a 32-lead TQFP package

with an operating temperature range of −40°C to 85°C.

I/O

Buffer

Input

DAC

Resistor

Network

Power

Down

Control

Logic

Control

Logic

REF

OUT

Sense

OUT

PD1PD0

REF

LDACRSTRSTSEL

AGND DGND

R/W

BTC/USB

Data I/O

DAC8541

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (25 pages)

PAGE 1
SLAS353 − DECEMBER 2001 FEATURES D Micropower Operation: 250 µA at 5 V AVDD D Power-On Reset to Min-Scale D 16-Bit Monotonic D Settling Time: 10 µs to ±0.003% FSR D 16-Bit Parallel Interface D On-Chip Output Buffer Amplifier With D D D D D D D Rail-to-Rail Operation Hardware Reset to Min-Scale or Mid-Scale Double-Buffered Architecture Asynchronous LDAC Control Data Readback Support 1.
PAGE 2
SLAS353 − DECEMBER 2001 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
PAGE 3
SLAS353 − DECEMBER 2001 electrical characteristics, DVDD = 1.8 V to 5.5 V; AVDD = 2.7 V to 5.5 V; RL = 2 kΩ to AGND; CL = 200 pF to AGND; all specifications –40°C to 85°C (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX 50 75 35 60 AGND AVDD 100 UNIT REFERENCE INPUT Reference current VREFH input range VREFL input range AVDD = VREFH = 5 V, VREFL = AGND AVDD = VREFH = 3.
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SLAS353 − DECEMBER 2001 CS R/W LDAC RST RSTSEL BTC/USB PD1 PD0 PBS PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 1 24 2 23 3 22 4 21 DAC8541 5 20 6 19 7 18 8 17 VOUT VOUTSense AGND VREFL VREFH AVDD DVDD DGND DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 9 10 11 12 13 14 15 16 Terminal Functions TERMINAL NAME NO. DB15−DB0 I/O DESCRIPTION 1−16 I/O DGND 17 I Digital ground DVDD 18 I Digital supply input, 1.8 V to 5.
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SLAS353 − DECEMBER 2001 timing characteristics, DVDD = 1.8 V to 5.5 V; AVDD = 2.7 V to 5.
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SLAS353 − DECEMBER 2001 tsu5 RSTSEL th5 tw6 RST tw7 ts +FS VOUT (RSTSEL = Low) Min-Scale −FS +FS VOUT Mid-Scale (RSTSEL = High) −FS Figure 2. Reset Timing TYPICAL CHARACTERISTICS This condition applies to all typical characteristics: VREFH = AVDD, VREFL = AGND, TA = 25°C (unless otherwise noted) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Linearity Error − LSB 64 AVDD = 2.7 V, TA = 85°C 48 32 16 0 −16 −32 −48 Differential Linearity Error − LSB −64 2 1.5 1 0.
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SLAS353 − DECEMBER 2001 TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Linearity Error − LSB 64 48 AVDD = 2.7 V, TA = 25°C 32 16 0 −16 −32 −48 Differential Linearity Error − LSB −64 2 1.5 1 0.5 0 −0.5 −1 −1.5 −2 0 8192 16384 24576 32768 40960 49152 57344 65535 Digital Input Code Figure 4 www.ti.
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SLAS353 − DECEMBER 2001 TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Linearity Error − LSB 64 AVDD = 2.7 V, TA = −40°C 48 32 16 0 −16 −32 −48 Differential Linearity Error − LSB −64 2 1.5 1 0.5 0 −0.5 −1 −1.5 −2 0 8192 16384 24576 32768 40960 Digital Input Code Figure 5 8 www.ti.
PAGE 9
SLAS353 − DECEMBER 2001 TYPICAL CHARACTERISTICS FULL-SCALE ERROR vs FREE-AIR TEMPERATURE ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE 20 20 AVDD = VREF = 5 V 10 AVDD = VREF = 2.7 V 5 0 −5 10 0 −15 −15 10 35 60 AVDD = 5 V −5 −10 −15 AVDD= 2.
PAGE 10
SLAS353 − DECEMBER 2001 TYPICAL CHARACTERISTICS ANALOG SUPPLY CURRENT vs DIGITAL INPUT CODE AIDD HISTOGRAM 2500 400 AI DD − Analog Supply Current −µ A AVDD = 2.7 V TA = 25°C Frequency 2000 1500 1000 500 0 Excluding Reference and Load Current. 350 300 AVDD = DVDD = 5 V 250 200 AVDD = DVDD = 2.7 V 150 100 50 0 100 150 200 250 300 AIDD − µA 350 0 400 50 AIDD − Power-Down Current − nA AI DD − Analog Supply Current −µ A Excluding Reference and Load Current.
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SLAS353 − DECEMBER 2001 TYPICAL CHARACTERISTICS EXITING POWER-DOWN MAJOR CARRY CODE CHANGE GLITCH VOUT − Output Voltage − 20 mV/div AVDD = VREF = 2.7 V Digital Code = 8000h Scope Trigger (5 V/div) VOUT (2 V/div) 0 2 4 6 8 10 12 14 AVDD = DVDD = VREF = 2.7 V Code 8000H to 7FFFH Glitch Occurs Every N × 4096 Code Boundary. 16 18 20 0 0.5 1 1.5 t − Time − µs 2 2.5 3 3.5 4 4.
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SLAS353 − DECEMBER 2001 TYPICAL CHARACTERISTICS FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME AVDD = 5 V AVDD = 2.
PAGE 13
SLAS353 − DECEMBER 2001 THEORY OF OPERATION D/A section The architecture of the DAC8541 consists of a string DAC followed by an output buffer amplifier. Figure 29 shows a generalized block diagram of the DAC architecture. VREFH = External Reference Voltage VOUTSense REF+ Resistor String REF− DAC Register − VOUT + VREFL = AGND Figure 29. Generalized DAC Architecture The input coding to the DAC8541 is set by the BTC/USB input to the device.
PAGE 14
SLAS353 − DECEMBER 2001 THEORY OF OPERATION resistor string The resistor string section is shown in Figure 30. It is simply a string of resistors, each of which has a value of R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This voltage is then presented to the output amplifier by closing one of the switches connecting the string to the amplifier.
PAGE 15
SLAS353 − DECEMBER 2001 THEORY OF OPERATION data format Table 2 details the input data format of the DAC8541. Two data I/O formats are available to the host interface. These two formats are binary 2s complement (BTC) and unipolar straight binary (USB). The BTC/USB input pin controls the format used by the DAC. The data format selected by the BTC/USB input is used for data written into the device as well as data that is read back from the DAC8541.
PAGE 16
SLAS353 − DECEMBER 2001 THEORY OF OPERATION power-down modes The DAC8541 utilizes four modes of operation. These modes are programmable via two inputs (PD1 and PD0) to the device. Table 3 shows how the state of these pins correspond to the mode of operation of the DAC8541. Table 3.
PAGE 17
SLAS353 − DECEMBER 2001 THEORY OF OPERATION analog and digital supplies The DAC8541 utilizes two separate supplies for operation. The analog supply (AVDD) powers the output buffer and DAC while the digital supply (DVDD) sets the I/O voltage thresholds. Refer to the device specification table for additional information. AVDD can operate from 2.7 V to 5.5 V while DVDD can independently function from 1.8 V to 5.5 V.
PAGE 18
SLAS353 − DECEMBER 2001 APPLICATION INFORMATION DAC8541 TMS320C5402 16 Bits D[15:0] D[15:0] AVDD AVDD 0.1 µF A[23:0] EN IOSTRB Address Decoder 10 µF CS DVDD DVDD 0.1 µF 10 µF R/W R/W LDAC XF(I/O) VOUTSENSE VOUT VOUT VREFH VREF VREFL 0.1 µF 1 to 10 µF AGND DGND (Other Connections Omitted for Clarity) Figure 33.
PAGE 19
SLAS353 − DECEMBER 2001 APPLICATION INFORMATION layout A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The following measures should be taken to assure optimum performance of the DAC8541. The DAC8541 offers dual-supply operation, as it can often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8541Y/250 TQFP PBS 32 250 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2 DAC8541Y/2K TQFP PBS 32 2000 330.0 16.4 7.2 7.2 1.5 12.0 16.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8541Y/250 TQFP PBS DAC8541Y/2K TQFP PBS 32 250 367.0 367.0 38.0 32 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.