Datasheet


SLAS353 − DECEMBER 2001
5
www.ti.com
timing characteristics, DV
DD
= 1.8 V to 5.5 V; AV
DD
= 2.7 V to 5.5 V; R
L
= 2 kΩ to AGND;
C
L
= 200 pF to AGND; all specifications –40°C to 85°C (unless otherwise noted)
MIN TYP MAX UNIT
t
w1
Pulse width: CS low for valid write 20 ns
t
su1
Setup time: R/W low before CS falling (see Note 4) 0 ns
t
su2
Setup time: data in valid before CS falling 0 ns
t
h1
Hold time: R/W low after CS rising (see Note 4) 10 ns
t
h2
Hold time: data in valid after CS rising 15 ns
t
w2
Pulse width: CS low for valid read 40 ns
t
su3
Setup time: R/W high before CS falling 30 ns
t
d1
Delay time: data out valid after CS falling 60 80 ns
t
h3
Hold time: R/W high after CS rising 10 ns
t
h4
Hold time: data out valid after CS rising 5 20 ns
t
su4
Setup time: LDAC rising after CS falling (see Note 4) 10 ns
t
d2
Delay time: CS low after LDAC rising 50 ns
t
w3
Pulse width: LDAC low 40 ns
t
w4
Pulse width: LDAC high 40 ns
t
w5
Pulse width: CS high (see Note 4) 80 ns
t
su5
Setup time: RSTSEL valid before RST rising 0 ns
t
h5
Hold time: RSTSEL valid after RST rising 20 ns
t
w6
Pulse width: RST low 40 ns
t
w7
Pulse width: RST high 40 ns
t
S
V
OUT
Settling time (settling time for a full scale code change) 10 µs
NOTE 4: Simplified operation: CS and W/R can be tied low if the DAC8541 is the only device on the bus and Read operation is not needed. In
this case, LDAC is still required to update the output of the DAC and t
su(4)
is from Data In Valid to LDAC Rising.
t
w1
t
w5
t
w2
t
su1
t
h1
t
su3
t
h3
t
h4
t
su2
t
h2
t
d1
t
su4
t
d2
t
w4
t
w3
t
s
±0.003% of FSR Error Bands
Data Out ValidData In Valid
CS
R/W
Data I/O
DB0−DB15
LDAC
V
OUT
Figure 1. Data Read/Write Timing