Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) TQFP 48

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FEATURES DESCRIPTION

APPLICATIONS

Interface

Logic

Power-On

Reset

Input

DAC

16 Bit

DAC

16 Bit

DAC

Buffer

DAC

Power-Down

Logic

D15

LDAC

RST

IOV

FBA

FBB

OUTA

OUTB

OUTC

OUTD

FBC

FBD

IOGND V

GND

REFA

+ V

REFA

− V

REFB

+ V

REFB

−

DAC8544

REFC

+ V

REFC

−V

REFD

−

R/W

DAC8544

SLAS420A – MAY 2004 – REVISED JUNE 2005

QUAD, 16-BIT, RAIL-TO-RAIL VOLTAGE OUTPUT, PARALLEL INTERFACE,

DIGITAL-TO-ANALOG CONVERTER

• Single Supply: +2.7 V to +5.5 V

The DAC8544 is a low-power, quad-channel, 16-bit,

• Micropower Operation: 950 µA @ 5 V

voltage output DAC. Its on-chip precision output

amplifier allows rail-to-rail voltage swing to be

• Rail-To-Rail Voltage Output

achieved at the output. The DAC8544 is 16-bit

• Ultralow Crosstalk: –110 dB

monotonic and offers exceptional absolute accuracy

• Settling Time: 10 µs To ±0.003% FSR

with ultralow crosstalk. The DAC8544 uses a 16-bit

parallel interface and features additional power-down

• 16-Bit Monotonic

function pins as well as hardware-enabled, synchron-

• Offset Error: ±0.3 mV

ous DAC updating and reset capability.

• Gain Error: ±1 mV

The DAC8544 requires an external reference voltage

• Total Error: ±3 mV

to set the output range of the DAC. The device

• Per-Channel V

REF+

, V

REF–

, V

Pins

incorporates a power-on-reset circuit that ensures

• Logic Compatible: +1.8 V to +5.5 V

that the DAC outputs power up at zero volt and

• Readback Capability

remains there until a valid write takes place. In

addition, the DAC8544 contains a power-down fea-

• Double Buffered Inputs

ture, accessed via PD pin, that reduces the current

• Simultaneous or Sequential Update

consumption of the device to 400 nA at 5 V. The

• Schmitt-Triggered Digital Inputs

power consumption is typically under 5 mW at

• Hardware Reset

= 5 V.

• 48-Lead TQFP Package

The DAC8544 is available in a 48-lead TQFP pack-

age with an operating temperature range of –40°C to

+105°C.

• Process Control

• Data Acquisition Systems

• Closed-Loop Servo Control

• PC Peripherals

• Optical Networking

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

PAGE 1
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 QUAD, 16-BIT, RAIL-TO-RAIL VOLTAGE OUTPUT, PARALLEL INTERFACE, DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • • • • • DESCRIPTION Single Supply: +2.7 V to +5.5 V Micropower Operation: 950 µA @ 5 V Rail-To-Rail Voltage Output Ultralow Crosstalk: –110 dB Settling Time: 10 µs To ±0.003% FSR 16-Bit Monotonic Offset Error: ±0.
PAGE 2
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 ELECTRICAL CHARACTERISTICS (continued) VDD = + 2.7 V to + 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted DAC8544 PARAMETER Slew Rate Capacitive Load Stability CONDITIONS MIN RL = 2 kΩ; CL <200 pF TYP MAX 1 RL = ∞ V/µs 470 RL = 2 kΩ UNITS pF 1000 pF Digital-to-Analog Glitch Impulse 20 nV-s Digital Feedthrough 0.
PAGE 4
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 TIMING CHARACTERISTICS IOVDD = 1.8 V to 5.5 V; VDD = 2.7 V to 5.
PAGE 5
DAC8544 www.ti.
PAGE 6
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS DAC8544 Pin 6 Mnemonic Function 1 VDD Analog supply voltage, +2.7 V to +5.5 V 2 GND Analog supply ground 3 IOGND Digital supply ground 4 IOVDD Digital supply +1.8 V to +5.
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DAC8544 www.ti.
PAGE 8
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) GAIN ERROR DISTRIBUTION (ACROSS MANY SAMPLES) 25 FULL SCALE ERROR DISTRIBUTION (ACROSS MANY SAMPLES) 25 TA = 25°C TA = 25°C 20 Percentage − % Percentage − % 20 15 10 5 15 10 5 0 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 Gain Error − mV 0.4 0.6 0.8 0 −1 1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.
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DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) SINK CURRENT AT NEGATIVE RAIL 0.15 SOURCE CURRENT AT POSITIVE RAIL 5 VREF = VDD −10 mV DAC Loaded With 0000 VDD = 5 V VDD = 2.7 V 0.1 V O − Output Voltage − V V O − Output Voltage − V 0.125 VDD = 5 V 0.075 0.05 4.95 4.9 4.85 0.025 VREF = VDD −10 mV DAC Loaded With FFFFH 4.
PAGE 10
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) HISTOGRAM OF CURRENT CONSUMPTION 0.8 4000 0.7 3500 IREF Included 3000 IDD = 5.5 V 0.6 VDD = 2.7 V Device Counts I DD − Supply Current − µ A SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 0.5 0.4 0.3 VIH = 2.7 V 0.2 2500 1500 1000 500 0.1 0 VDD = 5.
PAGE 11
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME 3.5 Large Signal VDD = VREF = 2.7 V Output Loaded With 2 kΩ and 200 pF to GND 2.5 1.50 VOUT − Output Voltage − V V O − Output Voltage − V 3 2 1.5 1 VDD = VREF = 2.7 V Output Loaded With 2 kΩ and 200 pF to GND 1.00 0.50 0.5 0 0.
PAGE 12
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) V O − Output Voltage − 5 mV/div FULL-SCALE SETTLING TIME (SMALL-SIGNAL NEGATIVE-GOING STEP) Small-Signal Settling Trigger Signal t − Time − 2 s/div Figure 29. THEORY OF OPERATION D/A SECTION The architecture of the DAC8544 consists of four string DACs followed by an output buffer amplifier.
PAGE 13
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 THEORY OF OPERATION (continued) To Output Amplifier VREF+ VREF– R R R R Figure 31. Resistor String OUTPUT AMPLIFIER The output buffer is capable of generating rail-to-rail voltages at its output, which gives an output range of 0 V to VREF+. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves.
PAGE 14
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 UPDATE SEQUENCE For regular operation, R/W pin should be kept low while CS is kept high. Then, the 16-bit digital data should be applied to the input bus. The channel selection should then be asserted by setting the A0 and A1 pins. Once the data is stable and the channels are selected the falling edge of CS enables the device and latches the data to the input register of the selected channel.
PAGE 15
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 When pin PD is high, the device works normally with its typical power consumption of 950 µA at VDD = 5 V. However, when PD pin is in low state, the device is in power-down mode, the supply current falls to 200 nA at VDD = 5 V (50 nA at VDD = 3 V), and the output is open circuit (high impedance). All analog circuitry is shut down when a power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down mode.
PAGE 16
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 MSP430F149 DAC8544 8 Bits 16 Bits P4[0:7] D[15:0] VDD VDD 8 Bits 0.1 F P5[0:7] 10 F CS P2:0 P2:1 R/W RST P2:2 IOVDD IOVDD 0.1 F P2:4 P2:5 P2:6 P2:7 LDAC PD VFB A1 A0 VREF − VOUT VREF + IOGND GND 10 F VOUT VREF 0.1 F 1 to 10 F (Other Pins Omitted for Clarity) Figure 32.
PAGE 17
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 R2 = 10 kΩ 5V R1 = 10 kΩ 5V − VREF + 10 µF 0.1 µF VOUT DAC8544 VFB + ±5 V OPA703 −5V VREF − (Other Pins Omitted for Clarity) Figure 34.
PAGE 18
DAC8544 www.ti.com SLAS420A – MAY 2004 – REVISED JUNE 2005 LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The following measures should be taken to assure optimum performance of the DAC8544. The DAC8544 offers dual-supply operation, as it can often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC8544IPFBR Package Package Pins Type Drawing TQFP PFB 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8544IPFBR TQFP PFB 48 1000 367.0 367.0 38.
PAGE 21
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.