Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VSSOP 8

DAC8550

OUT

ShiftRegister

GND

SYNC

SCLK

DACRegister

16-BitDAC

REF

REF(+)

PWB

Control

Resistor

Network

DAC8550

www.ti.com

SLAS476E –MARCH 2006–REVISED MARCH 2012

16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

Check for Samples: DAC8550

FEATURES

DESCRIPTION

234

• Relative Accuracy: 3LSB

The DAC8550 is a small, low-power, voltage output,

• Glitch Energy: 0.1nV-s

16-bit digital-to-analog converter (DAC). It is

• MicroPower Operation:

monotonic, provides good linearity, and minimizes

140μA at 2.7V

undesired code-to-code transient voltages. The

DAC8550 uses a versatile, 3-wire serial interface that

• Power-On Reset to Midscale

operates at clock rates of up to 30MHz and is

• Power Supply: +2.7V to +5.5V

compatible with standard SPI™, QSPI™,

• 16-Bit Monotonic Over Temperature

Microwire™, and digital signal processor (DSP)

interfaces.

• Settling Time: 10μs to ±0.003% FSR

• Low-Power Serial Interface with Schmitt-

The DAC8550 requires an external reference voltage

Triggered Inputs

to set its output range. The DAC8550 incorporates a

power-on reset circuit that ensures that the DAC

• On-Chip Output Buffer Amplifier with Rail-to-

output powers up at midscale and remains there until

Rail Output Amplifier

a valid write takes place to the device. The DAC8550

• Power-Down Capability

contains a power-down feature, accessed over the

• 2's Complement Input

serial interface, that reduces the current consumption

of the device to 200nA at 5V.

• SYNC Interrupt Facility

The low-power consumption of this device in normal

• Drop-In Compatible with DAC8531/01 and

operation makes it ideal for portable, battery-operated

DAC8551 (Binary Input)

equipment. Power consumption is 0.38mW at 2.7V,

• Available in a Tiny MSOP-8 Package

reducing to less than 1μW in power-down mode.

The DAC8550 is available in an MSOP-8 package.

APPLICATIONS

For additional flexibilty, see the DAC8551, a binary-

• Process Control

coded counterpart to the DAC8550.

• Data Acquisition Systems

• Closed-Loop Servo-Control

FUNCTIONAL BLOCK DIAGRAM

• PC Peripherals

• Portable Instrumentation

• Programmable Attenuation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI, QSPI are trademarks of Motorola, Inc.

3Microwire is a trademark of National Semiconductor.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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DA C8 550 DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC8550 FEATURES 1 • Relative Accuracy: 3LSB • Glitch Energy: 0.1nV-s • MicroPower Operation: 140μA at 2.7V • Power-On Reset to Midscale • Power Supply: +2.7V to +5.5V • 16-Bit Monotonic Over Temperature • Settling Time: 10μs to ±0.
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7V to 5.5V, –40°C to +105°C range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT CHARACTERISTICS (2) VO Output voltage range tSD Output voltage settling time SR Slew rate Capacitive load stability 0 To ±0.003% FSR, 1200h to 8D00h, RL = 2kΩ, 0pF < CL < 200pF 8 RL = 2kΩ, CL = 500pF RL = ∞ RL = 2kΩ VREF V 10 μs 12 μs 1.
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com PIN CONFIGURATION MSOP-8 (Top View) VDD 1 VREF 2 8 GND 7 DIN DAC8550 VFB 3 6 SCLK VOUT 4 5 SYNC PIN DESCRIPTIONS 4 PIN NAME 1 VDD Power-supply input, 2.7V to 5.5V. DESCRIPTION 2 VREF Reference voltage input. 3 VFB Feedback connection for the output amplifier. 4 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation. 5 SYNC Level-triggered control input (active LOW).
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 SERIAL WRITE OPERATION t9 t1 SCLK 1 24 t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB23 TIMING CHARACTERISTICS (1) DB0 DB23 (2) VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS: VDD = 5 V At TA = +25°C, unless otherwise noted. 6 4 2 0 -2 -4 -6 1.0 1.0 0.5 0.5 0 -0.5 -1.0 0 -0.5 6 4 2 0 -2 -4 -6 8192 16384 24576 32768 40960 49152 Digital Input Code 57344 65536 0 16384 24576 32768 40960 49152 Digital Input Code Figure 1. Figure 2. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105°C) ZERO-SCALE ERROR vs TEMPERATURE 57344 65536 10 VDD = 5V VREF = 4.
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS: VDD = 5 V (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE ERROR vs TEMPERATURE 0 SOURCE AND SINK CURRENT CAPABILITY 6 VDD = 5V VREF = 4.99V 5 DAC Loaded with FFFFh VOUT (mV) Error (mV) 4 -5 3 VDD = 5.5V VREF = VDD - 10mV 2 1 DAC Loaded with 0000h 0 -10 0 -40 40 80 120 0 2 4 6 8 Temperature (°C) I(SOURCE/SINK) (mA) Figure 5. Figure 6.
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS: VDD = 5 V (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL-SCALE SETTLING TIME: 5V RISING EDGE 1800 TA = 25°C, SCL Input (all other inputs = GND) VDD = VREF = 5.5V 1600 Trigger Pulse 5V/div 1400 IDD (mA) 1200 1000 VDD = 5V VREF = 4.
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS: VDD = 5 V (continued) At TA = +25°C, unless otherwise noted. GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE VOUT (500mV/div) VOUT (500mV/div) GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE VDD = 5V VREF = 4.096V From Code: 8000 To Code: 7FFF Glitch: 0.16nV-s Measured Worst Case VDD = 5V VREF = 4.096V From Code: 8000 To Code: 8010 Glitch: 0.04nV-s Time (400ns/div) Time (400ns/div) Figure 17. Figure 18.
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS: VDD = 5 V (continued) At TA = +25°C, unless otherwise noted. SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 98 VREF = VDD = 5V -1dB FSR Digital Input fS = 1MSPS Measurement Bandwidth = 20kHz 96 94 VDD = 5V VREF = 4.096V fOUT = 1kHz f = 1MSPS -10 -30 CLK Gain (dB) SNR (dB) POWER SPECTRAL DENSITY 92 90 -50 -70 88 -90 86 -110 84 -130 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 5.
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS: VDD = 2.7 V At TA = +25°C, unless otherwise noted. 6 4 2 0 -2 -4 -6 LE (LSB) 1.0 1.0 0.5 0.5 0 -0.5 VDD = 2.7V, VREF = 2.69V 0 -0.5 -1.0 0 6 4 2 0 -2 -4 -6 8192 16384 24576 32768 40960 49152 Digital Input Code 57344 65536 0 8192 16384 24576 32768 40960 49152 Digital Input Code Figure 26. Figure 27.
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE ERROR vs TEMPERATURE SOURCE AND SINK CURRENT CAPABILITY 5 3.0 VDD = 2.7V VREF = 2.69V 2.5 DAC Loaded with FFFFh 0 VOUT (mV) Error (mV) 2.0 1.5 VDD = 2.7V VREF = VDD - 10mV 1.0 -5 0.5 DAC Loaded with 0000h 0 -10 0 -40 40 80 120 0 4 6 8 I(SOURCE/SINK) (mA) Figure 30. Figure 31.
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE HALF-SCALE SETTLING TIME: 2.7V RISING EDGE Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div VDD = 2.7V VREF = 2.5V From Code: FFFF To Code: 0000 Falling Edge 0.5V/div Zoomed Falling Edge 1mV/div VDD = 2.7V VREF = 2.5V From Code: 4000 To Code: CFFF Rising Edge 0.
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued) At TA = +25°C, unless otherwise noted. GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE VOUT (5mV/div) VOUT (200mV/div) VDD = 2.7V VREF = 2.5V From Code: 8010 To Code: 8000 Glitch: 0.12nV-s VDD = 2.7V VREF = 2.5V From Code: 8000 To Code: 80FF Glitch: Not Detected Theoretical Worst Case Time (400ns/div) Time (400ns/div) Figure 42. Figure 43.
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 THEORY OF OPERATION DAC SECTION The architecture of the DAC8850 consists of a string DAC followed by an output buffer amplifier. Figure 45 shows the block diagram of the DAC architecture. VREF 50kW R 50kW R VFB 62kW DAC Register VOUT REF(+) Resistor String REF(-) To Output Amplifier R GND Figure 45.
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com than it does when it is LOW, SYNC should be idled LOW between write sequences for lowest power operation of the part. As mentioned above, it must be brought HIGH again just before the next write sequence. INPUT SHIFT REGISTER The input shift register is 24 bits wide, as shown in Figure 47. The first six bits are don't care bits.
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 POWER-DOWN MODES The DAC8550 supports four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table 1 shows how the state of the bits corresponds to the mode of operation of the device. impedance of the device is known while in powerdown mode. There are three different options.
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com MICROPROCESSOR INTERFACING MicrowireTM DAC8550 to 8051 Interface See Figure 50 for a serial interface between the DAC8550 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8550, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used.
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 APPLICATION INFORMATION 200 mA ) 5 V + 1.2 mA 5 kW USING THE REF02 AS A POWER SUPPLY FOR THE DAC8550 Due to the extremely low supply current required by the DAC8550, an alternative option is to use a REF02 +5V precision voltage reference to supply the required voltage to the device, as shown in Figure 53. (2) The load regulation of the REF02 is typically 0.005%/mA, resulting in an error of 299μV for the 1.2mA current drawn from it.
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DAC8550 SLAS476E – MARCH 2006 – REVISED MARCH 2012 www.ti.com LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8550 offers single-supply operation and is used often in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.
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DAC8550 www.ti.com SLAS476E – MARCH 2006 – REVISED MARCH 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2006) to Revision E Page • Changed low-level input voltage values in Electrcial Characteristics ................................................................................... 3 • Changed high-level input voltage values in Electrcial Characteristics ............................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DAC8550IBDGKR VSSOP DGK 8 DAC8550IBDGKT VSSOP DGK DAC8550IDGKR VSSOP DGK DAC8550IDGKT VSSOP DGK SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8550IBDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 DAC8550IBDGKT VSSOP DGK 8 250 210.0 185.0 35.0 DAC8550IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 DAC8550IDGKT VSSOP DGK 8 250 210.0 185.0 35.
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