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DAC8551

FEATURES DESCRIPTION

APPLICATIONS

16-BitDAC

OUT

ShiftRegister

GND

SYNC

SCLK

REF

DACRegister

Ref(+)

PWDControl

Resistor

Network

DAC8551

SLAS429B – APRIL 2005 – REVISED OCTOBER 2006

16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

• Relative Accuracy: 3LSB

The DAC8551 is a small, low-power, voltage output,

16-bit digital-to-analog converter (DAC). It is

• Glitch Energy: 0.1nV-s

monotonic, provides good linearity, and minimizes

• MicroPower Operation:

undesired code-to-code transient voltages. The

140 µ A at 2.7V

DAC8551 uses a versatile 3-wire serial interface that

• Power-On Reset to Zero

operates at clock rates to 30MHz and is compatible

with standard SPI™, QSPI™, Microwire™, and

• Power Supply: +2.7V to +5.5V

digital signal processor (DSP) interfaces.

• 16-Bit Monotonic Over Temperature

The DAC8551 requires an external reference voltage

• Settling Time: 10 µ s to ± 0.003% FSR

to set its output range. The DAC8551 incorporates a

• Low-Power Serial Interface with

power-on-reset circuit that ensures the DAC output

Schmitt-Triggered Inputs

powers up at 0V and remains there until a valid write

• On-Chip Output Buffer Amplifier with

takes place to the device. The DAC8551 contains a

Rail-to-Rail Operation

power-down feature, accessed over the serial

interface, that reduces the current consumption of

• Power-Down Capability

the device to 200nA at 5V.

• Binary Input

The low-power consumption of this device in normal

• SYNC Interrupt Facility

operation makes it ideally suited for portable, battery-

• Drop-In Compatible With DAC8531/01

operated equipment. The power consumption is

and DAC8550 (2's Complement Input)

0.38mW at 2.7V, reducing to less than 1 µ W in

power-down mode.

• Available in a Tiny MSOP-8 Package

The DAC8551 is available in an MSOP-8 package.

For additional flexibilty, see the DAC8550, a 2's

• Process Control

complement-input counterpart to the DAC8551.

• Data Acquisition Systems

• Closed-Loop Servo-Control

FUNCTIONAL BLOCK DIAGRAM

• PC Peripherals

• Portable Instrumentation

• Programmable Attenuation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI, QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
DA C8 DAC8551 551 SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • • Relative Accuracy: 3LSB Glitch Energy: 0.1nV-s MicroPower Operation: 140µA at 2.7V Power-On Reset to Zero Power Supply: +2.7V to +5.5V 16-Bit Monotonic Over Temperature Settling Time: 10µs to ±0.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7V to 5.5V,and –40°C to +105°C range, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREF V 10 µs OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time 0 To ±0.003% FSR, 0200h to FD00h, RL = 2kΩ, 0pF < CL < 200pF 8 RL = 2kΩ, CL = 50 pF Slew rate Capacitive load stability RL = ∞ RL = 2kΩ 12 µs 1.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 PIN CONFIGURATION DGK PACKAGE MSOP-8 (Top View) VDD 1 VREF 2 8 GND 7 DIN DAC8551 VFB 3 6 SCLK VOUT 4 5 SYNC PIN DESCRIPTIONS 4 PIN NAME 1 VDD Power supply input, 2.7V to 5.5V. DESCRIPTION 2 VREF Reference voltage input. 3 VFB Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally. 4 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 SERIAL WRITE OPERATION t9 t1 SCLK 1 24 t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB23 DB0 DB23 TIMING CHARACTERISTICS (1) (2) VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5 V At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (-40°C) VDD = 5V, VREF = 4.99V 6 4 2 0 -2 -4 -6 LE (LSB) LE (LSB) 6 4 2 0 -2 -4 -6 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) 1.0 DLE (LSB) DLE (LSB) 1.0 0.5 0 -0.5 -1.0 6 4 2 0 -2 -4 -6 0 -0.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5 V (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs TEMPERATURE 300 250 VDD = VREF = 5V 250 VREF = VDD = 5V 200 IDD (mA) IDD (mA) 200 Reference Current Included 150 150 100 100 50 50 0 0 0 -40 8192 16384 24576 32768 40960 49152 57344 65536 80 Figure 7. Figure 8.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5 V (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE SETTLING TIME: 5V FALLING EDGE HALF-SCALE SETTLING TIME: 5V RISING EDGE Trigger Pulse 5V/div Trigger Pulse 5V/div VDD = 5V VREF = 4.096V From Code: FFFF To Code: 0000 Falling Edge 1V/div Rising Edge 1V/div Zoomed Falling Edge 1mV/div VDD = 5V VREF = 4.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5 V (continued) At TA = +25°C, unless otherwise noted. GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE VOUT (5mV/div) VOUT (500mV/div) VDD = 5V VREF = 4.096V From Code: 8010 To Code: 8000 Glitch: 0.08nV-s VDD = 5V VREF = 4.096V From Code: 8000 To Code: 80FF Glitch: Not Detected Theoretical Worst Case Time (400ns/div) Time (400ns/div) Figure 19. Figure 20.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 5 V (continued) At TA = +25°C, unless otherwise noted. OUTPUT NOISE DENSITY 350 VDD = 5V VREF = 4.99V Code = 7FFFh No Load Voltage Noise (nV/ÖHz) 300 250 200 150 100 100 1k 10k Frequency (Hz) Figure 25.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7 V At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (-40°C) 6 4 2 0 -2 -4 -6 VDD = 2.7V, VREF = 2.69V LE (LSB) LE (LSB) 6 4 2 0 -2 -4 -6 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) 1.0 DLE (LSB) DLE (LSB) 1.0 0.5 0 -0.5 -1.0 6 4 2 0 -2 -4 -6 0 -0.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs TEMPERATURE 180 250 VDD = VREF = 2.7V 160 VREF = VDD = 2.7V 200 140 Reference Current Included IDD (mA) IDD (mA) 120 100 80 150 100 60 40 50 20 0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 -40 -10 20 50 80 110 Temperature (°C) Digital Input Code Figure 32.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued) At TA = +25°C, unless otherwise noted. HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE VDD = 2.7V VREF = 2.5V From Code: CFFF To Code: 4000 Falling Edge 0.5V/div VOUT (200mV/div) Trigger Pulse 2.7V/div VDD = 2.7V VREF = 2.5V From Code: 7FFF To Code: 8000 Glitch: 0.08nV-s Zoomed Falling Edge 1mV/div Time (400ns/div) Figure 38. Figure 39.
PAGE 14
DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued) At TA = +25°C, unless otherwise noted. VOUT (5mV/div) GLITCH ENERGY: 2.7V, 256LSB STEP, FALLING EDGE VDD = 2.7V VREF = 2.5V From Code: 80FF To Code: 8000 Glitch: Not Detected Theoretical Worst Case Time (400ns/div) Figure 44.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 THEORY OF OPERATION DAC SECTION VREF The DAC8551 architecture consists of a string DAC followed by an output buffer amplifier. Figure 45 shows a block diagram of the DAC architecture. VREF 50kW RDIVIDER VREF 2 50kW VFB R 62kW DAC Register REF (+) Register String REF (-) VOUT R To Output Amplifier (2x Gain) GND Figure 45.
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DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum of 33ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. As previously mentioned, it must be brought HIGH again just before the next write sequence. INPUT SHIFT REGISTER The input shift register is 24 bits wide, as shown in Figure 47. The first six bits are don't care bits.
PAGE 17
DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 POWER-DOWN MODES The DAC8551 supports four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table 1 shows how the state of the bits corresponds to the mode of operation of the device. power-down mode. There are three different options. The output is connected internally to GND through a 1kΩ resistor, a 100kΩ resistor, or it is left open-circuited (High-Z).
PAGE 18
DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 MICROPROCESSOR INTERFACING MicrowireTM DAC8551 to 8051 Interface See Figure 50 for a serial interface between the DAC8551 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8551, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used.
PAGE 19
DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 APPLICATION INFORMATION The total typical current required (with a 5kΩ load on the DAC output) is: 200mA ) 5V + 1.2mA 5kW (2) USING THE REF02 AS A POWER SUPPLY FOR THE DAC8551 Due to the extremely low supply current required by the DAC8551, an alternative option is to use the REF02 (+5 V precision voltage reference) to supply the required voltage to the device, as illustrated in Figure 53. The load regulation of the REF02 is typically 0.
PAGE 20
DAC8551 www.ti.com SLAS429B – APRIL 2005 – REVISED OCTOBER 2006 LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8551 offers single-supply operation, and it often is used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DAC8551IADGKR VSSOP DGK 8 DAC8551IADGKT VSSOP DGK DAC8551IDGKR VSSOP DGK DAC8551IDGKT VSSOP DGK SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8551IADGKR VSSOP DGK 8 2500 367.0 367.0 35.0 DAC8551IADGKT VSSOP DGK 8 250 210.0 185.0 35.0 DAC8551IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 DAC8551IDGKT VSSOP DGK 8 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.